This paper introduces a concept of provably detected defects that are identified through topology analysis and AMS verification database inquiry. The main purpose is to associate detected status to such defect without simulation, thereby reducing the size of defect simulation campaign. The proposed approach is a combination of fundamental and empirical rule-based set targeting relevant steps that are part of regular design sign-off. The feasibility is illustrated on an industrial product that is currently undergoing final stages of the tape-out, with the results complying to the current status of upcoming IEEE P2427 standard in development.

The paper proposes a method for identifying undetectable defects in mixed-signal circuits to exclude them from further consideration in defect campaigns. The method uses an equivalence checker to generate counterexamples or prove the undetectability of a defect.

This article presents a new approach to automate the setup of the design equations of the manual analog design process. Its main contribution is a comprehensive hierarchical performance equation library (HPEL) for op-amps. The HPEL makes the setup of design equations independent of the topology. Based on the library and the functional block recognition method in Abelet al.(2020), analytical performance models for various op-amp topologies are automatically instantiated. The method is currently designed for basic op-amps. In this article, we use the method to size different op-amp topologies. Experimental results featuring four circuits are presented. The HPEL has also been integrated into a structural synthesis method featuring several thousand op-amp topologies (Abel and Graeb, 2021).

This article presents a method to automatically synthesize the structure and initial sizing of an operational amplifier. It is positioned between approaches with fixed design plans and a small search space of structures and approaches with generic structural production rules and a large search space with technically impractical structures. The presented approach develops a hierarchical composition graph based on functional blocks that spans a search space of thousands of technically meaningful structure variants for single-output, fully differential, and complementary operational amplifiers. The search algorithm is a combined heuristic and enumerative process. The evaluation is based on circuit sizing with a library of behavioral equations of functional blocks. Formalizing the knowledge of functional blocks in op-amps for structural synthesis and sizing inherently reduces the search space and lessens the number of created topologies not fulfilling the specifications. Experimental results for the three op-amp classes are presented. An outlook how this method can be extended to multi-stage op-amps is given.

Extracting structural information of a design is one crucial aspect of many circuit verification and synthesis methods. State-of-the-art structure recognition methods use a predefined building block library to identify the basic building blocks in a circuit. However, the capability of these algorithms is limited by the scope, correctness and completeness of the provided library. This paper presents a new method to automatically generate the recognition rules required to identify a given circuit topology in a large design. Device pairs are grouped into building blocks by analyzing their characteristics, e.g., their connectivity, to enable a structure recognition as unambiguous as possible. The resulting blocks are consecutively assembled to larger blocks until the full building block description of the given topology has been established. Building block libraries dedicated to one specific topology type, e.g., operational amplifiers, can be obtained by applying the method to its basic version, subsequently extending the generated library by the additional elements required to identify its topology variants using the presented method. Experimental results for six folded cascode amplifier and five level shifter topologies are given.

This paper present a new method to automatically synthesize operational amplifiers. The topology synthesis is based on a functional block modeling. Every op-amp consists of hierarchical functional blocks whose behaviors are describable with analytical equations. Synthesizing the topologies based on functional blocks allows to use the sizing of the topologies during the synthesis process to lessen the number of topologies created not fulfilling the specifications. This makes this method different to previous methods and reduces the time needed to find a large variety of topologies fulfilling a given set of specifications. The paper presents the first prototype of the method.

This paper presents a new method to automate the initial sizing of operational amplifiers. The method emulates the manual design procedure. The sizing task is formulated as a constraint programming problem. Two new algorithms are introduced: First, a hierarchical structural analysis of functional blocks that automatically sets up the analytical equations for the sizing. And second, a heuristic to guide branching process of a constraint programming solver. We achieve a reproduction of the manual proceeding of designers and at the same time an automation of the set-up of the design problem, reducing the set-up effort from months to seconds. 16 topologies, including different variants of two-stage, folded-cascode, telescopic and symmetrical op-amps, are considered at this time. In this paper, experimental results for a two-stage op-amp and a folded-cascode op-amp are presented to show the effectiveness of the approach.