VLDB 2026 Research / reviewers in the wild / expert
Chih-Chen Yeh
dblp:258/6401
· DBLP profile ↗
2ranked-venue papers
0as first author
2since 2021 · last 2024
0000-0003-1556-0521ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 54% Memory systems · 46% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › processing-in-memory
computing-in-memory |
0.8 | 1 | 2024 | ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory · IEEE Trans. Computers 2024 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › in-memory computing accelerator
computing-in-memory CNN accelerator |
0.8 | 1 | 2024 | ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory · IEEE Trans. Computers 2024 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.8 | 1 | 2024 | ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory · IEEE Trans. Computers 2024 |
Memory systems
processing-in-memory |
0.8 | 1 | 2024 | ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory · IEEE Trans. Computers 2024 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
CNN accelerator |
0.2 | 1 | 2024 | ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory · IEEE Trans. Computers 2024 |
Methods — techniques the papers use, named apart from their topics
zero-skipping · 0.8systolic dataflow · 0.8channel swapping · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-MemoryabstractAmong several emerging architectures, computing in memory (CIM), which featuresin-situ analog computation, is a potential solution to the data movement bottleneck of the Von Neumann architecture for artificial intelligence (AI). Interestingly, more strengths of CIM significantly different from in-situ analog computation are not widely known yet. In this work, we point out thatmutually stationary vectors (MSVs), which can be maximized by introducingassociativityto CIM, are another inherent power unique to CIM. By MSVs, CIM exhibits significant freedom to dynamically vectorize the stored data (e.g., weights) to perform agile computation using the dynamically formed vectors. We have designed and realized an SA-CIM silicon prototype and corresponding architecture and acceleration schemes in the TSMC 28 nm process. More specifically, the contributions of this paper are fivefold: 1) We identify MSVs as new features that can be exploited to improve the current performance and energy challenges of the CIM-based hardware. 2) We propose SA-CIM to enhance MSVs (input-reordering flexibility) for skipping the zeros, small values, and sparse vectors. 3) We propose channel swapping to enhance the zero-skipping technique. 4) We propose a transposed systolic dataflow to efficiently conduct conv3×3 while being capable of exploiting input-skipping schemes. 5) We propose a design flow to search for optimal aggressive skipping scheme setups while satisfying the accuracy loss constraint. The proposed ISSA architecture improves the throughput by 1.91× to 2.97× speedup and the energy efficiency by 2.5× to 4.2×. Yun-Chen Lo, Jun-Shen Wu, Chia-Chun Wang, Yu-Chih Tsai, Chih-Chen Yeh, Wen-Chien Ting, Ren-Shuo Liu |
IEEE Trans. Computers | 5 |
| 2022 | ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network AcceleratorsabstractAmong several emerging architectures, computing in memory (CIM), which features in-situ analog computation, is a potential solution to the data movement bottleneck of the Von Neumann architecture for artificial intelligence (AI). Interestingly, more strengths of CIM significantly different from in-situ analog computation are not widely known yet. In this work, we point out that mutually stationary vectors (MSVs), which can be maximized by introducing associativity to CIM, are another inherent power unique to CIM. By MSVs, CIM exhibits significant freedom to dynamically vectorize the stored data (e.g., weights) to perform agile computation using the dynamically formed vectors. Yun-Chen Lo, Chih-Chen Yeh, Jun-Shen Wu, Chia-Chun Wang, Yu-Chih Tsai, Wen-Chien Ting, Ren-Shuo Liu |
ICCAD | 2 |