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Johannes Kath

dblp:259/3583 · DBLP profile ↗
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2ranked-venue papers
0as first author
1since 2021 · last 2021
0000-0001-5508-3788ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware accelerators and domain-specific architectures · 45% Performance modeling and evaluation · 41% Reconfigurable computing and FPGAs · 14%
Artificial intelligence
1 paper
Efficient and distributed learning · 100%

Topics — the 9 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation
benchmarking
0.622021
Evaluation of Optimized CNNs on Heterogeneous Accelerators Using a Novel Benchmarking Approach · IEEE Trans. Computers 2021
Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach · FPGA 2020
Machine learning › Efficient and distributed learning
model compression
0.512021
Evaluation of Optimized CNNs on Heterogeneous Accelerators Using a Novel Benchmarking Approach · IEEE Trans. Computers 2021
Machine learning › Efficient and distributed learning › model compression
pruning and quantization
0.512021
Evaluation of Optimized CNNs on Heterogeneous Accelerators Using a Novel Benchmarking Approach · IEEE Trans. Computers 2021
Performance modeling and evaluation › benchmarking › computer architecture benchmarking
accelerator benchmarking
0.512021
Evaluation of Optimized CNNs on Heterogeneous Accelerators Using a Novel Benchmarking Approach · IEEE Trans. Computers 2021
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator
0.512021
Evaluation of Optimized CNNs on Heterogeneous Accelerators Using a Novel Benchmarking Approach · IEEE Trans. Computers 2021
Hardware accelerators and domain-specific architectures › machine learning accelerator › DNN inference
CNN inference
0.412020
Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach · FPGA 2020
Reconfigurable computing and FPGAs › FPGA accelerator
FPGA accelerator design
0.412020
Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach · FPGA 2020
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.412020
Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach · FPGA 2020
Performance modeling and evaluation › system-level analysis › architecture evaluation
accelerator comparison
0.112020
Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach · FPGA 2020

Methods — techniques the papers use, named apart from their topics

quantization · 1.4pruning · 1.4benchmarking · 1.0
YearPublicationVenuePosition
2021 Evaluation of Optimized CNNs on Heterogeneous Accelerators Using a Novel Benchmarking Approach
abstract
Numerous algorithmic optimization techniques have been proposed to alleviate the computational complexity of convolutional neural networks. Given the broad selection of AI accelerators, it is not obvious which approach benefits from which optimization most. The design space includes a large number of deployment settings (batch sizes, power modes, etc.) and unclear measurement methods. This research provides clarity into this design space, leveraging a novel benchmarking approach. We provide a theoretical evaluation of different CNNs and hardware platforms, focusing on understanding the impact of pruning and quantization as primary optimization techniques. We benchmark across a spectrum of FPGA, GPU, TPU, and VLIW processors for systematically pruned and quantized neural networks (ResNet50, GoogLeNetv1, MobileNetv1, a VGG derivative, a multilayer perceptron) over many deployment options, considering power, latency, and throughput at a specific accuracy. Our findings show that channel pruning is most effective and works across most hardware platforms, with speedups directly correlated to the reduction in compute load, while FPGAs benefit the most from quantization. Pruning and quantization are orthogonal, and yield optimal design points when combined. Further in-depth results can be found at our web portal, where we share all experimental data, provide data analytics, and invite the community to contribute.
Michaela Blott, Nicholas J. Fraser, Giulio Gambardella, Lisa Halder, Johannes Kath, Zachary Neveu, Yaman Umuroglu, Alina Vasilciuc, Miriam Leeser, Linda Doyle
IEEE Trans. Computers5
2020 Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach
abstract
Numerous algorithmic optimization techniques have been proposed to alleviate the computational complexity of convolutional neural networks (CNNs). However, given the broad selection of inference accelerators, it is not obvious which approach benefits from which optimization and to what degree. In addition, the design space is further obscured by many deployment settings such as power and operating modes, batch sizes, as well as ill-defined measurement methodologies. In this paper, we systematically benchmark different types of CNNs leveraging both pruning and quantization as the most promising optimization techniques leveraging a novel benchmarking approach. We evaluate a spectrum of FPGA implementations, GPU, TPU and VLIW processor, for a selection of systematically pruned and quantized neural networks (including ResNet50, GoogleNetv1, MobileNetv1, a VGG derivative, and a multilayer perceptron) taking the full design space into account including batch sizes, thread counts, stream sizes and operating modes, and considering power, latency, and throughput at a specific accuracy as figure of merit. Our findings show that channel pruning is effective across most hardware platforms, with resulting speedups directly correlated to the reduction in compute load, while FPGAs benefit the most from quantization. FPGAs outperform regarding latency and latency variation for the majority of CNNs, in particular with feed-forward dataflow implementations. Finally, pruning and quantization are orthogonal techniques and yield the majority of all optimal design points when combined. With this benchmarking approach, both in terms of methodology and measured results, we aim to drive more clarity in the choice of CNN implementations and optimizations.
Michaela Blott, Johannes Kath, Lisa Halder, Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Miriam Leeser, Linda Doyle
FPGA2