VLDB 2026 Research / reviewers in the wild / expert
Yingran Tan
dblp:259/3622
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2020
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 100% | |
| Artificial intelligence
1 paper |
Efficient and distributed learning · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures › machine learning accelerator
CNN accelerator |
0.4 | 1 | 2020 | LPAC: A Low-Precision Accelerator for CNN on FPGAs · FPGA 2020 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › CNN accelerator
FPGA-based CNN accelerator |
0.4 | 1 | 2020 | LPAC: A Low-Precision Accelerator for CNN on FPGAs · FPGA 2020 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
low-bit quantization accelerator |
0.4 | 1 | 2020 | LPAC: A Low-Precision Accelerator for CNN on FPGAs · FPGA 2020 |
Machine learning › Efficient and distributed learning
model compression |
0.1 | 1 | 2020 | LPAC: A Low-Precision Accelerator for CNN on FPGAs · FPGA 2020 |
Machine learning › Efficient and distributed learning › model compression
quantization |
0.1 | 1 | 2020 | LPAC: A Low-Precision Accelerator for CNN on FPGAs · FPGA 2020 |
Methods — techniques the papers use, named apart from their topics
DSP mapping · 0.94a4w quantization · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | LPAC: A Low-Precision Accelerator for CNN on FPGAsabstractLow bit quantization of neural network is required on edge devices to achieve lower power consumption and higher performance. 8bit or binary network either consumes a lot of resources or has accuracy degradation. Thus, a full-process hardware-friendly quantization solution of 4A4W (activations 4bit and weights 4bit) is proposed to achieve better accuracy/resource trade-off. It doesn't contain any additional floating operations and achieve accuracy comparable to full-precision. We also implement a low-precision accelerator for CNN (LPAC) on the Xilinx FPGA, which takes full advantage of its DSP by efficiently mapping convolutional computations. Through on-chip reassign management and resource-saving analysis, high performance can be achieved on small chips. Our 4A4W solution achieves 1.8x higher performance than 8A8W and 2.42x increase in power efficiency under the same resource. On ImageNet classification, the accuracy has a gap less than 1% to full-precision in Top-5. On the human pose estimation, we achieve 261 frames per second on ZU2EG, which is 1.78x speed up compared to 8A8W and the accuracy has only 1.62% gap to full-precision. This proves that our solution has better universality. Tiantian Han, Xijie Jia, Guangdong Liu, Pingbo An, Yingran Tan, Lingzhi Sui, Shaoxia Fang, Dongliang Xie, Michaela Blott |
FPGA | 8 |