VLDB 2026 Research / reviewers in the wild / expert
Tiantian Han
dblp:259/3846
· DBLP profile ↗
3ranked-venue papers
1as first author
1since 2021 · last 2021
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 2 · 1 first-author · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 2 · 1 first-author · 1 since 2021Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Artificial intelligence
3 papers |
Efficient and distributed learning · 67% Face, body and person analysis · 33% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 100% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Machine learning › Efficient and distributed learning
model quantization |
0.5 | 1 | 2021 | Improving Low-Precision Network Quantization via Bin Regularization · ICCV 2021 |
Computer vision › Face, body and person analysis
face detection |
0.4 | 1 | 2020 | ProgressFace: Scale-Aware Progressive Learning for Face Detection · ECCV (6) 2020 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
CNN accelerator |
0.4 | 1 | 2020 | LPAC: A Low-Precision Accelerator for CNN on FPGAs · FPGA 2020 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › CNN accelerator
FPGA-based CNN accelerator |
0.4 | 1 | 2020 | LPAC: A Low-Precision Accelerator for CNN on FPGAs · FPGA 2020 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
low-bit quantization accelerator |
0.4 | 1 | 2020 | LPAC: A Low-Precision Accelerator for CNN on FPGAs · FPGA 2020 |
Machine learning › Efficient and distributed learning
model compression |
0.1 | 1 | 2020 | LPAC: A Low-Precision Accelerator for CNN on FPGAs · FPGA 2020 |
Machine learning › Efficient and distributed learning › efficient training
progressive learning |
0.1 | 1 | 2020 | ProgressFace: Scale-Aware Progressive Learning for Face Detection · ECCV (6) 2020 |
Machine learning › Efficient and distributed learning › model compression
quantization |
0.1 | 1 | 2020 | LPAC: A Low-Precision Accelerator for CNN on FPGAs · FPGA 2020 |
Methods — techniques the papers use, named apart from their topics
DSP mapping · 0.94a4w quantization · 0.9quantization-aware training · 0.5bin regularization · 0.5scale-aware learning · 0.4progressive learning · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2021 | Improving Low-Precision Network Quantization via Bin RegularizationabstractModel quantization is an important mechanism for energy-efficient deployment of deep neural networks on resource-constrained devices by reducing the bit precision of weights and activations. However, it remains challenging to maintain high accuracy as bit precision decreases, especially for low-precision networks (e.g., 2-bit MobileNetV2). Existing methods have been explored to address this problem by minimizing the quantization error or mimicking the data distribution of full-precision networks. In this work, we propose a novel weight regularization algorithm for improving low-precision network quantization. Instead of constraining the overall data distribution, we separably optimize all elements in each quantization bin to be as close to the target quantized value as possible. Such bin regularization (BR) mechanism encourages the weight distribution of each quantization bin to be sharp and approximate to a Dirac delta distribution ideally. Experiments demonstrate that our method achieves consistent improvements over the state-of-the-art quantization-aware training methods for different low-precision networks. Particularly, our bin regularization improves LSQ for 2-bit MobileNetV2 and MobileNetV3-Small by 3.9% and 4.9% top-1 accuracy on ImageNet, respectively. Tiantian Han, Dong Li 0025 |
ICCV | 1 |
| 2020 | ProgressFace: Scale-Aware Progressive Learning for Face Detection
Jiashu Zhu, Dong Li 0025, Tiantian Han |
ECCV (6) | 3 |
| 2020 | LPAC: A Low-Precision Accelerator for CNN on FPGAsabstractLow bit quantization of neural network is required on edge devices to achieve lower power consumption and higher performance. 8bit or binary network either consumes a lot of resources or has accuracy degradation. Thus, a full-process hardware-friendly quantization solution of 4A4W (activations 4bit and weights 4bit) is proposed to achieve better accuracy/resource trade-off. It doesn't contain any additional floating operations and achieve accuracy comparable to full-precision. We also implement a low-precision accelerator for CNN (LPAC) on the Xilinx FPGA, which takes full advantage of its DSP by efficiently mapping convolutional computations. Through on-chip reassign management and resource-saving analysis, high performance can be achieved on small chips. Our 4A4W solution achieves 1.8x higher performance than 8A8W and 2.42x increase in power efficiency under the same resource. On ImageNet classification, the accuracy has a gap less than 1% to full-precision in Top-5. On the human pose estimation, we achieve 261 frames per second on ZU2EG, which is 1.78x speed up compared to 8A8W and the accuracy has only 1.62% gap to full-precision. This proves that our solution has better universality. Tiantian Han, Xijie Jia, Guangdong Liu, Pingbo An, Yingran Tan, Lingzhi Sui, Shaoxia Fang, Dongliang Xie, Michaela Blott |
FPGA | 2 |