Pedestrian detection is an important task in autonomous surveillance systems. Despite the rapid progress in pedestrian detection field, detecting occluded pedestrians remains a challenging task due to the great variations in occluded pedestrians appearance and the drastic loss of pedestrian information in some severe cases. In this paper, we tackle the occlusion problem by proposing a multi-branch pedestrian detection model based on center and scale prediction framework. The proposed model employs features extracted from full pedestrian’s body as well as its upper, middle, and lower body parts using four detection branches. This multi-branch approach ensures that data representing the true pedestrian appearances, whether they are partially or completely visible, can dominate the final decision-making, minimizing the interference of non-pedestrian data in the detection. Furthermore, to implement the proposed model, the visibility of different pedestrian parts is appropriately annotated, which facilitates the training process. The final decision is made based on the four MB-CSP branches outputs, using a proposed fusing method, named Boosted Identity Aware-Non Maximum Suppression. On heavy occlusion settings, the proposed model resulted in the miss rates of 27.83%, 47.29% and 33.3% for Caltech-USA, Citypersons and EuroCity Persons datasets, respectively.

LCMOS, a harvest-use light-powered scheme for standard CMOS circuits based on photogenerated currents in the drain-substrate PN junction of both PMOS and NMOS transistors is introduced. PMOS and NMOS bulks are ground-connected so the generated currents induce symmetrical positive and negative voltage at the PMOS and NMOS sources, respectively. Applying this approach to a CMOS inverter ring oscillator in 150 nm technology, simulations show that nearly 1 Vpp signal range can be obtained. The operation of a simple 4-bit counter is also illustrated. The light-powering technique can be applied almost directly to digital standard cells in ultra-low-power applications with modest processing speed requirements.

In this paper, first, a new Laplacian kernel is developed to integrate into it the anisotropic behavior to control the process of forward diffusion in horizontal and vertical directions. It is shown that, although the new kernel reduces the process of edge distortion, it nonetheless produces artifacts in the processed image. After examining the source of this problem, an analytical scheme is devised to obtain a spatially varying kernel that adapts itself to the diffusivity function. The proposed spatially varying Laplacian kernel is then used in various nonlinear diffusion filters starting from the classical Perona-Malik filter to the more recent ones. The effectiveness of the new kernel in terms of quantitative and qualitative measures is demonstrated by applying it to noisy images.

Edge detection plays a critical role in image processing The performance of an edge detection algorithm can be affected by serious noise & intensity inhomogeneities. In this paper, a method aiming at detecting edge of image with varieties of gradient signal degradation is proposed. The method comprises two steps. The first step is to perform adaptive histogram equalization to improve the signal contrast in a discriminative manner. To this end, the histogram of the input image is analysed and the irregularity of image intensity, if there is any, is identified and removed by using a contrast limited adaptive histogram equalization technique. The following step is a gradient modulation filtering process with the modulation factor determined by the local intensity. The simulation results comprising subjective and objective analysis show that the pro- posed method is applicable and effective to detect edges of low-quality images.

Reducing the leakage power in embedded SRAM memories is critical for low-power applications. Raising the source voltage of SRAM cells in standby mode reduces the leakage currents effectively. However, in order to preserve the state of the cell in standby mode, source voltage cannot be raised beyond a certain level. The maximum source voltage of an SRAM cell is determined by its hold stability in a particular process corner. Hence, in order to achieve the maximum leakage reduction, the source voltage of each individual cell must be raised up to its maximum safe level. However, any cell-based technique realizing this would be practically not feasible. In this paper, we propose an SRAM leakage reduction technique, referred to as adaptive sleep transistor biasing, which automatically fine-tunes the source voltage of individual memory blocks to their optimum level. Thus, maximum leakage savings can be expected while data is safely retained during standby mode. Preliminary study shows that the proposed scheme has the potential of providing substantial saving in leakage power over those by using the conventional techniques.

Sample-hold is one of the basic non-linear functions in analog-mixed circuits. Switching noise can critically affect the operation for such a function, particularly in case of current sample-hold, if no effective measures are taken to reduce it. In this paper, a method for an efficient reduction of the effect of the switching noise is proposed. The principle of this method is to bias a transistor in the operation region where it has a weak transconductance and an attenuating voltage transfer characteristic, and use this device to absorb the switching noise, in order to protect the critical circuit nodes. This method can be implemented very easily without need of any devices requiring linearity or precision. A current memory cell is designed with this method and the simulation results show that the switching noise causes much less negative effect to the circuit operation.

In this paper, an efficient VLSI architecture for a fast computation of the 2-D discrete wavelet transform (DWT) is proposed. The architecture employing a three-stage cascade in pipeline mode enhances the computing time by appropriately distributing the overall computational load among the three stages and by incorporating parallelism at various hierarchies of the architecture. The computing time is further enhanced by making use of a scheme for the equalization of the data paths in terms of the delays in the computational blocks of the architecture. A Verilog simulation of the proposed architecture is carried out to demonstrate the superior performance of the architecture.

The work presented in this paper is about the design of current-controlled oscillators (ICO). Two ICOs are proposed. Aiming at reducing the duration of the short-circuit currents caused by slowly-changing voltages in the circuits, signal conversion blocks are introduced to generate sharp pulses. In this way, the power efficiency of the circuits is improved, which leads to an extensive performance improvement of the circuits. Both ICOs can operate over a frequency range from 100 KHz to 900 MHz. The quality of the output waveforms before buffers is good and over the entire frequency range the rise/fall time is consistently short. The power dissipation of the ICOs is very low, the same as that of a 5-stage current-starving ring oscillator. Moreover, the scheme of the ICOs allows an easy adjustment of the duty cycle of the output pulse signals. A simple digital control structure of the duty cycle has also been proposed.

Visually tracking a real-world target with an image sensor is widely applicable in robotics and human-computer interaction but is a computationally intensive task. Smart image sensors can make use of integrated motion detection circuits for target tracking, but algorithms for tracking complex, real-world targets are usually not suited to smart sensor implementations. We propose a sensor structure for tracking targets that have complex spatial frequency patterns and varying velocities. In this structure only basic motion detection circuits are used, however the distance between sensing elements is varied in order to vary the filtering properties of the system to be sensitive to a broad range of spatial frequencies and velocities. Simulation results show that it is possible to be selectively sensitive to both the different spatial frequencies of a target and to its varying velocity.

This paper proposes a hardware architecture of a video noise estimtion algorithm capable of real-time processing. The objectives consist of adapting a computationally demanding noise estimation algorithm to a synthesizable VHDL implementation and achieving real-time performance. This Structure-oriented noise estimation method considers image structure to find intensity-homogeneous blocks Subsequently, these blocks are included in the averaging process to estimate the noise variance. Generating worst-case estimation error of 3 dB, this spatial noise reduction method is reliable for highly noisy and textured images. The proposed architecture provides a satisfactory compromise between area and processing speed. Furthermore, parameterization of the architecture allows additional flexibility with the scaling of mask sizes that can operate on 3×3 or 5×5 blocks of pixels. The proposed design is targeted to an FPGA device and estimates the noise variance over an interlaced PAL video sequence.

In this paper, an approach of implementing voltage-insensitive and space-efficient capacitances has been proposed. It tackles capacitive elements related to the thin dielectric layers available in fabrication technologies of integrated circuits. It makes the use of the voltage-independent ones, such as the overlap capacitances of MOS transistors, and the voltage-dependency of the capacitances attached to the same circuit nodes are minimized by device geometric sizing and voltage biasing. In the case of using the MOS transistor gate dielectric layer, the capacitance is scaled by the width of the gate area of the transistor employed. As the transistor feature size is of sub-micron, the unit capacitance can be very small and the capacitances can be scaled easily and precisely, which facilitates a significant down-scale of the circuit geometric dimension, operation delay and, at the same time, power dissipation. As an example of application of the proposed approach, a charge-mode parallel D/A converter is proposed in this paper.

A thinning process suitable for pixel array circuit implementation is presented. The process is designed to have the computations in parallel and to include only simple logic operations so that the structure of each pixel is simple and the array circuit has an acceptable resolution. Simulation with images of different patterns, including fingerprints, demonstrate that the proposed thinning process is effective, and its results meet the requirement of minutia detection for identification. The structure of such a pixel array circuit is designed as an implementation example and is presented. The circuit has four interconnections per pixel, and can be implemented in a digital CMOS process.

In this paper, we propose a flexible architecture that performs the computation of the discrete wavelet transform, requiring a small memory space and is capable of operating at high sampling rate. The architecture employs two filtering blocks to compute the transform and one buffer to store the intermediate results. Each filtering block has two processing units that operate independently in parallel using a two-phase scheduling. An efficient scheme for the synchronization of the data flow among the three blocks is provided in order to minimize the buffer size and increase the speed of operation. Verilog and HSPICE simulation results are presented to show that the proposed architecture is more efficient for the computation of a fully decomposed discrete wavelet transform with high-tap filters than some other existing architectures in terms of their areas and speed of operations.

An architecture for a VLSI sensory-motor system is presented. It makes use of ideas from behavior-based robotics and biology to achieve an obstacle avoidance behavior in an unstructured environment. Sensory-motor coordination is achieved by correlating a map of the visual field with a map which represents the robot's body. Rapid decision making is facilitated by a post-receptor foveation scheme which permits the fixation of the open pathway and the localization of obstacles through spatial gradients. The foveation scheme uniquely combines space-variant processing with the possibility for high-resolution, per-pixel spatio-temporal operations across the focal plane. Only a small number of computationally simple operations are used per-pixel, potentially leading to implementations with small pixels and high fill-factors.

We present in this paper a current mediated active pixel sensor (APS) with variable image size and resolution for power saving, electronic zooming, and data reduction at the sensor level. The circuit can perform averaging of output signals in blocks of adjacent pixels (kernels) of size 1/spl times/1, 2/spl times/2 and 4/spl times/4, allowing data reduction without aliasing effects. To achieve this, a current approach is used, thus enabling high speed operation and low power supply capacity. A novel fixed pattern noise (FPN) reduction scheme using a compact circuitry is presented. The circuit compensates for pixel transconductance mismatch in addition to offset error via analog to digital conversion reference current scaling. Hspice simulations using parameters of a 0.35 /spl mu/m CMOS process illustrate the advantage of the new technique over usual correlated double sampling (CDS) in current mode sensors. Parallel integrated analog to digital converters (ADC), a data line-buffer and digital control complete the circuit making data transmission easy and simplifying hardware needed for using the image sensor.

An accurate CMOS current mirror circuit operating in a very weak current range is proposed to compensate for transistor mismatch. A procedure that automatically adjusts the gate-to-source voltages of the transistor pair is implemented to compensate for the physical parameter mismatch in order to ensure an acceptable accuracy in the current operation. The proposed design operates with less than 1% error for a 20% geometric mismatch in the current range of 1 nA to 1 /spl mu/A. This circuit may be implemented using a CMOS single poly technology.

We propose an adaptive optical sensor circuit performing a linear incident-light-to-voltage conversion using the channel-length-modulation effect. The sensitivity of the sensor adapts automatically to the signal level, so that a dynamic range of six decades is reachable. The process of the conversion does not involve any current integration. No multiple clocks are required in the operation. The circuit does not involve any linear devices. The circuit can be, therefore, implemented densely in silicon using a single-poly technology. Moreover, the development of deep-sub-micron technology favors the design and implementation of the sensor circuit.