This paper analyzes the conventional uses of magnetic switch cores to drive matrix stores in both current-driven and voltage-driven modes. A new method of using switch cores is proposed and analyzed which offers, at the cost of replacing in every selection line the usual switch-core and terminating resistor by two smaller cores, intrinsic pulse shaping and amplitude regulation, and much reduced power dissipation, particularly in the driving stages. Constructional details of an application of the new method to drive a store 100×80×10 are given, and waveforms for this store are shown. All address decoding and driving are performed by 34 transistors. A model of a multiple coincidence store 101×101 with a cycle time of 1 μsec has also been constructed; details are given.

Memories using toroidal ferrite cores with cycle timies less than a microsecond are described; the selection ratio is increased by the use of biasing and the multiple coincidence principles of Minnick and Ashenhurst.1 It is shown that this mode of operation leads to important changes in the structure of the store; in particular, the classical core switch does not fulfll the new requirements. The ``two-core switch'' is then briefly described; it permits an elegant and economic solution of the problems arising at high selection ratios. Details of the design and operation of memories embodying these ideas are given; it is shown, for example, that standard core memory matrices can be used very efficiently at a selection ratio of 3:1 to achieve a cycle time of 2 microseconds. Further illustrations are given from a model of a 100×100 store operated at 4:1 and 7:1 selection ratios, and it is shown that a store of 10,000 8-bit characters with a cycle time of 0.25 microsecond is feasible.