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Ahmed S. Desouki

dblp:26/1596 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 50% Electronic design automation · 50%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits		 0.011994
A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation
design optimization		 0.011994
A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Integrated circuit design › digital circuit design › CMOS circuit design
digital CMOS circuits		 0.011994
A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation › physical design › timing optimization
propagation delay optimization		 0.011994
A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994

Methods — techniques the papers use, named apart from their topics

base doping profile optimization · 0.0
YearPublicationVenuePosition
1994 A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays
abstract
Proposes an optimization procedure for the bipolar base doping profile for a high-speed BiCMOS circuit. This procedure aims to achieve the minimum propagation delay time, taking the power supply, the load capacitance, and the bipolar device layout into consideration. For a small load capacitance, the peak base doping concentration and the base width should be as small as possible. However, for a high load capacitance, the optimized base doping profile can vary under the emitter area constraint. Utilizing this optimization procedure, it will be shown that the propagation delay time can be reduced by more than 30% at the same MOS current (I/sub MOS/=1 mA) through the coordinated reduction of both the vertical doping profile and the horizontal dimensions of the bipolar transistor, with the power supply voltage scaled from 5 to 3.3 V.>
Ahmed S. Desouki, Young-June Park, Hong-Shick Min
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1