Task mapping has been a hot topic in multiprocessor system-on-chip software design for decades. During the mapping process, load balance (LB) and communication optimization have been two important performance optimization factors. This paper studies the relations between LB, interprocessor communications, and communication pipeline technique during the mapping process, and proposes an integer linear programming (ILP)-based static task mapping approach, which considers both LB and communication optimization. The approach consists of an optimized ILP model for task mapping with fewer variables compared to previous ILP mapping works. Moreover, to enhance the scalability of the ILP task mapping, the task-processor-cluster algorithm is proposed to reduce the scale of the task graph and the number of processors and then solve the coarse-grained input by the ILP mapping. To increase the adaptability of the ILP task mapping, the improved augmented E-constraint method is further integrated with the ILP formulations to select the best mapping for different applications. Experimental results on a 2/4/8/16/24-CPU platform of both synthetic and real-life benchmarks demonstrate the efficiency of the proposed approach.

The emerging market of the Internet of Things is constrained by the energy-efficiency of each layers having a role in Wireless Personal Area Networks (WPANs). In this context, adaptivity is a key technique to address the need of low-power consumption in unpredictable environments, by providing at any time a low-margin operating mode. For this purpose, the paper presents an IEEE 802.15.4 digital baseband with a tunable computation subsampling mechanism built-in. The described architecture, simulated in a 65 nm LP-CMOS process, drains only 82.9 μA in average at its best operating point against 208 μA in normal mode. Thus, it enables a power consumption reduction of up to 58 % that can be exploited in case of favorable receiving conditions, as part of a self-adaptive wireless network.

Communication frequency is increasing with the growing complexity of emerging embedded applications and the number of processors in the implemented multiprocessor SoC architectures. In this article, we consider the issue of communication cost reduction during multithreaded code generation from partitioned Simulink models to help designers in code optimization to improve system performance. We first propose a technique combining message aggregation and communication pipeline methods, which groups communications with the same destinations and sources and parallelizes communication and computation tasks. We also present a method to apply static analysis and dynamic emulation for efficient communication buffer allocation to further reduce synchronization cost and increase processor utilization. The existing cyclic dependency in the mapped model may hinder the effectiveness of the two techniques. We further propose a set of optimizations involving repartition with strongly connected threads to maximize the degree of communication reduction and preprocessing strategies with available delays in the model to reduce the number of communication channels that cannot be optimized. Experimental results demonstrate the advantages of the proposed optimizations with 11--143% throughput improvement.

Efficient design of multiprocessor system-on-chip (MPSoC) requires early, fast, and accurate performance estimation techniques. In this paper, we present new techniques based on fine-grained code analysis to estimate accurate performance during simulation of MPSoC transaction accurate models. First, a GCC profiling tool is applied in the native simulation process. Based on the profiling result, an instruction analyzer of the target CPU architecture is proposed to analyze the cycle cost of C code under estimation. In addition, a memory analyzer is used to further estimate memory access latency including both instruction/data cache time cost and global memory access cycles. Both data and instruction cache models are proposed to estimate cache miss penalty, and a segment-based strategy is adopted to update the cache models more efficiently. Furthermore, an equalized access model is presented to imitate the memory access behavior of processors for estimating global memory access latency caused by bus contention and memory bandwidth. We have applied these techniques on an H.264 decoder application with different hardware architectures. The experimental results show that applying these techniques can obviously improve estimation accuracy of transaction accurate models close to that of the virtual prototype models, with a tolerable overhead on simulation speed.

SUMMARY Three‐dimensional networks‐on‐chip (3D NoC) are rising as a good approach to well managed complex interconnections in 3D multi‐processor system‐on‐chip (MPSoC). This paper introduces a new router in order to enhance throughput and latency compared to classic 3D mesh NoC. The proposed router is hierarchical as it is composed of two completely decoupled modules: one for inter‐layer communication and one for intra‐layer communication. It is fully implemented in asynchronous logic to allow low latency transfer. Synthesis and extrapolation results show that the hierarchical router is competitive with the classic 3D mesh in terms of area and power. Throughput and latency evaluation is performed using a SystemC‐TLM NoC simulator. Simulations' results show that the proposed hierarchical router can outperform the 3D mesh by more than 25% in terms of throughput and latency in the case of transpose traffic. Copyright © 2012 John Wiley & Sons, Ltd.

To address the problem of prohibitive costs of advanced technologies, one solution consists in reusing masks to address a wide range of systems. This could be achieved by a modular circuit that can be stacked to build 3D systems with processing performance adapted to several applications. This paper focuses on 4G wireless telecom applications. We propose a basic circuit that meets the SISO (Single Input Single Output) transmission mode. By stacking multiple instances of this same circuit, it will be possible to address several MIMO (Multiple Input Multiple Output) modes. The proposed circuit is composed of several processing units interconnected by a 3D NoC and controlled by a host processor. Compared to a 2D reference platform, the proposed circuit keeps at least the same performance and power consumption in the context of 4G telecom applications, while reducing total mask cost.

The last decade was dominated by HW-SW convergence where designers learned to combine hardware and software design to cope with the increased demand of lower cost and increased performances. This starting decade will be dominated by the convergence between design technology (HW and SW) and fabrication technologies. In fact more and more designs require a deep knowledge of technology characteristics to reach the required performances. On the other side, design technologies are more and more used to overcome fabrication process imperfection and to improve yield. This talk will first explain the achievements in HW-SW convergence and SoC design. Then, it will address the fabrication technology trends and challenges to deal with this convergence.

Applications like 4G baseband modem require single-chip implementation to meet the integration and power consumption requirements. These applications demand a high computing performance with real-time constraints, low-power consumption and low cost. With the rapid evolution of telecom standards and the increasing demand for multi-standard products, the need for flexible baseband solutions is growing. The concept of Multi-Processor System-on-Chip (MPSoC) is well adapted to enable hardware reuse between products and between multiple wireless standards in the same device. Heterogeneous architectures are well known solutions but they have limited flexibility. Based on the experience of two heterogeneous Software Defined Radio (SDR) telecom chipsets, this paper presents the homoGENEous Processor arraY (GENEPY) platform for 4G applications. This platform is built with Smart ModEm Processors (SMEP) interconnected with a Network-on-Chip. The SMEP, implemented in 65nm low-power CMOS, can perform 3.2 GMAC/s with 77 GBits/s internal bandwidth at 400MHz. Two implementations of homogeneous GENEPY are compared to a heterogeneous platform in terms of silicon area, performance and power consumption. Results show that a homogeneous approach can be more efficient and flexible than a heterogeneous approach in the context of 4G Mobile Terminals.

Current multiprocessor systems on chip (MPSoC) architectures integrate a massive number of IPs that need to exchange data in complex and diverse synchronization ways. The key challenge when designing MPSoC is that the communication architecture needs to be decided at the beginning of the design, before all the details about mapping the application on the architecture are known. These early decisions cause two difficulties: how to select the best communication architecture and how to estimate the effect of mapping the application onto the communication resources. In this paper, we propose high level communication models that allow early accurate performance estimation of both communication architecture and communication mapping. We applied the proposed modeling methods to analyze the impact on performance in case of two network topologies and several communication mapping schemes for the H.264 Encoder application.

Summary form only given. Multicore SoCs integrate an increasing number of heterogeneous programmable units and sophisticated communication interconnects. Unlike classic computers, the design of SoC includes the building of application specific architecture and specific interconnect and other hardware components required to execute the software for a well defined class of applications. In this case, the programming model hides both hardware and software interfaces that may include sophisticated communication and synchronisation concepts to handle parallel programs running on the processors. This embedded tutorial introduces the key technologies for the design of such complex devices.

The multiprocessor system-on-chip (MPSoC) uses multiple CPUs along with other hardware subsystems to implement a system. A wide range of MPSoC architectures have been developed over the past decade. This paper surveys the history of MPSoCs to argue that they represent an important and distinct category of computer architecture. We consider some of the technological trends that have driven the design of MPSoCs. We also survey computer-aided design problems relevant to the design of MPSoCs.

Current multimedia applications demand complex heterogeneous multiprocessor architectures with specific communication infrastructure in order to achieve the required performances. Programming these architectures usually results in writing separate low-level code for the different processors (DSP, microcontroller), implying late global validation of the overall application with the hardware platform. We propose a platform-based software design flow able to efficiently use the resources of the architecture and allowing easy experimentation of several mappings of the application onto the platform resources. We use a high-level environment to capture both application and architecture initial representations. An executable software stack is generated automatically for each processor from the initial model. The software generation and validation is performed gradually corresponding to different software abstraction levels. Specific software development platforms (abstract models of the architecture) are generated and used to allow debugging of the different software components with explicit hardware-software interaction. We applied this approach on a multimedia platform, involving a high performance DSP and a RISC processor, to explore communication architecture and generate an efficient executable code for a multimedia application. Based on automatic tools, the proposed flow increases productivity and preserves design quality.

At high abstraction level, multi-processor system-on-chip (SoC) designs are specified as assembling of IP's which can be hardware or software. The refinement of communication between these different IP's, known as hardware/software interfaces, is widely seen as the design bottleneck due to their complexity. In order to perform early design validation and architecture exploration, flexible executable models of these interfaces are needed at different abstraction levels. In this paper, we define a unified methodology to implement executable models of the hardware/software interface based on SystemC. The proposed formalism based on the concept of services gives to this approach the flexibility needed for architecture exploration and the ability to be used in automatic generation tools. A case study of hardware/software interface modeling at the transaction accurate level is presented. Experimental results show that this method allows higher simulation speed with early performance estimation.

Estimation tools are a key component of system-level methodologies, enabling a fast design space exploration. Estimation of software performance is essential in current software-dominated embedded systems. This work proposes an integrated methodology for system design and performance analysis. An analytic approach based on neural networks is used for high-level software performance estimation. At the functional level, this analytic tool enables a fast evaluation of the performance to be obtained with selected processors, which is an essential task for the definition of a "golden" architecture. From this architectural definition, a tool that refines hardware and software interfaces produces a bus-functional model. A virtual prototype is then generated from the bus-functional model, providing a global, cycle-accurate simulation model and offering several features for design validation and detailed performance analysis. Our work thus combines an analytic approach at functional level and a simulation-based approach at bus functional level. This provides an adequate trade-off between estimation time and precision. A multiprocessor platform implementing an MPEG4 encoder is used as case study, and the analytic estimation results in errors only up to 17% when compared to the virtual platform simulation. On the other hand, the analytic estimation takes only 17 seconds, against 10 minutes using the cycle-accurate simulation model.

Multimedia applications require heterogeneous multiprocessor architectures with specific I/O components in order to achieve computation and communication performances. The different processors run different software stacks, which are composed by the application s tasks and a hardware dependent software (HDS). The HDS contains an operating system, a specific communication library and a hardware abstraction layer (HAL), granting accesses to hardware resources. Building these software stacks may be the trouble maker of the MP-SoC design process when trying to reduce its time-to-market. In this paper, we present our application software generation flow and tools starting from a high level application model. They are able to handle heterogeneous MP-SoC, running multiple software stacks while using different operating systems and communication models. The application software generation tool builds the application s sofware stacks by producing optimized and multi-tasked C code and using a flexible operating system and communication programming interfaces management. In order to validate the effectiveness of our approach, we generated the software stacks of a Motion JPEG decoder, partitioned and mapped on an off-the-shelf multimedia platform.

System-level design methodologies have been introduced as a solution to handle the design complexity of embedded multiprocessor SoC (MPSoC) systems. In this paper we describe a system-level design flow starting from Simulink specification, focusing on concurrent hardware and software design and verification at four different abstraction levels: Simulink Combined Algorithm and Architecture Model (CAAM), Virtual Architecture, Transaction-accurate Model and Virtual Prototype. We used two multimedia applications, Motion-JPEG and H.264, to evaluate this design flow. Experimental results show that our design flow can generate various MPSoC architectures from Simulink CAAM correctly and efficiently, allowing processor and task design space exploration at different abstraction levels.

Software synthesis from a data-flow model has been a very promising technique, especially for multimedia applications with contradicting requirements of high design complexity and fast time-to-market. In a dataflow model, buffer size is pessimistically determined through static analysis, thus results in large memory overhead even with optimization techniques such as buffer sharing and scheduling. So, reducing buffer size is one of the key issues of data-flow models. In this work, we propose a novel software synthesis technique to reduce buffer size through control-flow decomposition. We first traverse the control-flow within each actor of a data-flow graph and decompose it into a set of multiple execution paths. Then we transform the actor such that only one of the paths is executed at one invocation of the actor. The new actor may have to be invoked many times to complete the behavior of the original actor. By proper decomposition, we can make the new actor consume/produce much smaller amount of input/output data for each invocation, thereby reducing the input/output buffer size drastically. We automate the process of transformation and show the efficiency of the proposed approach through experiments with image/video multimedia applications.

Heterogeneous MPSoCs present unique opportunities for emerging embedded applications, which require both high-performance and programmability. Although, software programming for these MPSoC architectures requires tedious and error-prone tasks, thereby automatic code generation tools are required. A code generation method based on fine-grain specification can provide more design space and optimization opportunities, such as exploiting fine-level parallelism and more efficient partitions. However, when partitioned, fine-grain models may require a large number of inter-processor communications, decreasing the overall system performance. This paper presents a Simulink-based multithread code generation method, which applies Message Aggregation optimization technique to reduce the number of inter-processor communications. This technique reduces the communication overheads in terms of execution time by reduction on the number of messages exchanged and in terms of memory size by the reduction on the number of channels. The paper also presents experiment results for one multimedia application, showing performance improvements and memory reduction obtained with Message Aggregation technique.

Considering current time-to-market pressures, IP reuse is mandatory for the design of complex embedded systems-on-chip (SoC). The integration of IP components into a given design is the most complex task in the whole reuse process. This paper describes the IP integration approach implemented in the ROSES design environment, which presents a unique combination of features that enhance IP reuse: automatic assembly of interfaces between heterogeneous software and hardware IP components; easy adaptation to different on-chip communication structures and bus and core standards; generation of customized and minimal OSs for programmable components; and an architecture-independent high-level API embedded into SystemC that makes application software independent from system implementation. Application code is written by using communication functions available in this API. ROSES automatically assembles wrappers that implement these functions, such that the application code does not need to be modified in order to run in the final synthesized system.

This paper proposes the use of a high-level architecture exploration method for different MPEG4 video encoders using different customization parameters. The targeted architecture is a heterogeneous MP-SoC which may include up 2 coarse grain SIMD (task level SIMD) subsystems to perform the computations. The customization parameters are related to video resolution, frame rate, communication network, level of parallelism and CPU types. These parameters are determined during the high-level architecture exploration, by estimating the architecture performances at early stages of the design flow. Experiments shows that the error factor of these high-level performances estimations are less than 10% compared to those obtained with final manually implemented RTL architecture. This method was used successfully for exploration of different MPEG4 architecture configurations with different customization parameters. We consider these experiments a breakthrough because they show how a complex design can be mastered through a set of pragmatic choices.

Architectures with multiple programmable cores are becoming more attractive for video codec applications because they can provide highly concurrent compilation and support multiple video standards and a shorter time-to-market. To find an efficient SW code for the multiple core architecture for a video codec application, it is very important to easily explore the design space by generating a SW code automatically from its functional model. We introduce Abstract Clock Synchronous Model (ACSM) for functional modeling of video codec applications. The ACSM can easily represent both parallelism and conditionals, which are common in video codec applications. By applying ACSM to an H.264 baseline decoder on single core architecture, we reduced the execution time and the number of external memory accesses by 32 % and 46 % respectively compared to traditional dataflow model.

Reduction of the on-chip memory size is a key issue in video codec system design. Because video codec applications involve complex algorithms that are both data-intensive and control-dependent, memory optimization based on global and precise analysis of data and control dependency is required. We generate a memory-efficient C code from a restricted Simulink model, which can represent both data and control dependency explicitly, by applying two buffer memory optimization techniques: copy removal and buffer sharing. Copy removal is performed while parsing the Simulink model. Buffer sharing requires global scheduling and formal lifetime analysis. Experimental results on an H.264 video decoder show that the buffer memory size and execution time of the C code generated by the proposed method are 71% and 32% less than those of the C code produced by Simulink's C code generator, respectively. When compared to the hand written C code, the memory size was reduced by 27% while its execution time was increased by only 3%.

For the design of classic computers the Parallel programming concept is used to abstract HW/SW interfaces during high level specification of application software. The software is then adapted to an existing multiprocessor platforms using a low level software layers that implement the programming model. Unlike classic computers, the design of heterogeneous MPSoC includes also building the processors and other kind of hardware components required to execute the software. In this case, the programming model hides both hardware and software refinements. This paper deals with parallel programming models to abstract both hardware and software Interfaces in the case of heterogeneous MPSoC design. Different abstraction levels will be needed. For the long term, the use of higher level programming models will open new vistas for optimization and architecture exploration like CPU/RTOS tradeoffs.

editorial Free Access Share on Guest editorial: Concurrent hardware and software design for multiprocessor SoC Guest Editors: Ahmed Jerraya View Profile , Trevor Mudge View Profile Authors Info & Claims ACM Transactions on Embedded Computing SystemsVolume 5Issue 2May 2006 pp 259–262https://doi.org/10.1145/1151074.1151075Published:01 May 2006Publication History 1citation685DownloadsMetricsTotal Citations1Total Downloads685Last 12 Months21Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

The Intellectual Property (IP)-based design for high-throughput dedicated digital signal processing (DSP) systems is obviously an important issue for improving not only design productivity, but also design from the high level of abstraction. However, in some cases, synthesizable register transfer level (RTL) model obtained by an automatic assembly of RTL IPs can be wrong due to delays induced by implementation constraints. In this paper, we present the formalization of the problem and propose an approach called automatic delay correction method (ADCM) to solve the problem without inserting an extra interface circuitry. The approach automatically inserts control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IPs. The delays may be managed by registers or by counters included in the control structure. A formal theory of ADCM is developed to guide the implementation and guarantee optimal solutions in latency and area. Through experiments with synthetic example and three real world high-throughput DSP circuits, we also show the effectiveness of our approach.

Current and future SoC will contain an increasing number of heterogeneous multiprocessor subsystems combined with a complex communication architecture to meet flexibility, performance and cost constraints. The early validation of such complex MP-SoC architectures is a key enabler to manage this complexity and thus to enhance design productivity.In this paper, we describe an abstract, high level CPU subsystem model that captures the specificities of such MP-SoC architectures, along with a timed co-simulation environment to perform early exploration of the entire HW/SW design. The model is based on the Hardware Abstraction Layer (HAL) concept allowing the validation of complex applications written on top of real-life operating systems. Experimentation with a MPEG4 application proves the interest of the proposed methodology.

In the design of a heterogeneous multiprocessor system on chip, we face a new design problem; scheduler implementation. In this paper, we present an approach to implementing a static scheduler, which controls all the task executions and communication transactions of a system according to a pre-determined schedule. For the scheduler implementation, we consider both intra-processor and inter-processor synchronization. We also consider scheduler overhead, which is often neglected. In particular, we address the issue of centralized implementation versus distributed implementation. We investigate the pros and cons of the two different scheduler implementations. Through experiments with synthetic examples and a real world multimedia application, we show the effectiveness of our approach.

The Growing requirement on the correct design of a high performance DSP system in short time force us to use IP's in many design. In this paper, we propose an efficient IP block based design environment for high throughput VLSI Systems. The flow generates SystemC Register Transfer Level (RTL) architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement process inserts automatically control structures to treat delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The experimentations show that the approach can produce efficient RTL architecture and allow a huge save of time.

One major challenge in System-on-Chip (SoC) design is the definition and design of interfaces between hardware and software. Traditional ASIC designer and software designer model HW/SW interface twice. Using two separate models introduces a discontinuity between hardware and software. This paper introduces a unified HW/SW component model to describe different parts of HW/SW interface at different abstraction levels. The benefits of using the proposed model are two fold: first, it provides a single model to present system design from abstract specification to mixed HW/SW implementation and second, it enables full system simulation at different abstraction level during refinement flow.

Massive data transfer encountered in emerging multimedia embedded applications requires architecture allowing both highly distributed memory structure and multiprocessor computation to be handled. The key issue that needs to be solved is then how to manage data transfers between large numbers of distributed memories. To overcome this issue, our paper proposes a scalable Distributed Memory Server (DMS) for multiprocessor SoC (MPSoC). The proposed DMS is composed of: (1) high-performance and flexible memory service access points (MSAPs), which execute data transfers without intervention of the processing elements, (2) data network, and (3) control network. It can handle direct massive data transfer between the distributed memories of an MPSoC. The scalability and flexibility of the proposed DMS are illustrated through the implementation of an MPEG4 video encoder for QCIF and CIF formats. The experiments show clearly how DMS can be adapted to accommodate different SoC configurations requiring various data transfer bandwidths. Synthesis results show that bandwidth can scale up to 28.8 GB/sec.

This paper reports a case study of multiprocessor SoC (MPSoC) design of a complex video encoder, namely OpenDivX. OpenDivX is a popular version of MPEG4. It requires massive computation resources and deals with complex data structures to represent video streams. In this study, the initial specification is given in sequential C code that had to be parallelized to be executed on four different processors. High level programming model, namely Message Passing Interface (MPI) was used to enable inter-task communication among parallelized C code. A four processor hardware prototyping platform was used to debug the parallelized software before final SoC hardware is ready. The targeting of abstract parallel code using MPI to the multiprocessor architecture required the design of an additional hardware-dependent software layer to refine the abstract programming model. The design was made by a team work of three types of designer: application software, hardware-dependent software and hardware platform designers. The collaboration was necessary to master the whole flow from the specification to the platform.The study showed that HW/SW interface debug was the most time-consuming step. This is identified as a potential killer for application-specific MPSoC design. To further investigate the ways to accelerate the HW/SW interface debug, we analyzed bugs found in the case study and the available debug environments. Finally, we address a debug strategy that exploits efficiently existing debug environments to reduce the time for HW/SW interface debug.

Most system-on-chip (SoC) design methodologies promote the reuse of pre-designed (hardware, software, and functional) components. However, as these components are heterogeneous, their integration requires complex interface sub-systems. These sub-systems can also be constructed by assembling pre-designed basic interface components. Hence, SoC design and validation involves component composition techniques to create hardware, software, and functional interface sub-systems by assembling basic interface components. We propose a unified methodology for automatic component integration that allows designers to reuse pre-designed components effectively. We also present ROSES, a design flow that uses this methodology to generate hardware, software, and functional interface sub-systems automatically starting from a system-level architectural model.

In conventional multiprocessor SoC (MPSoC) design methods, we find two problems: lack of SW code portability and lack of early SW validation. The problems cause a long design cycle. To resolve them, we present a concept of two-layer hardware-dependent software (HdS). The presented HdS consists of hardware abstraction layer to abstract the sub-system architecture and SoC abstraction layer to abstract the global MPSoC architecture. During the exploration of global and sub-system architectures, the application programming interfaces of presented two-layer HdS allow to keep the SW independent from architectural change. The simulation models of two-layer HdS enable to validate the entire system including the SW and HW design early in the design steps. We show the effectiveness of the presented methodology in the MPSoC architecture exploration of an OpenDiVX encoder system design.

An embedded system is an application specific electronic subsystem used in a larger system such as an appliance, an instrument or a vehicle. An embedded system is generally made of software (called embedded software) and a hardware platform. The evolution of technologies is enabling to the integration of complex platforms in a single chip (called system-on-chip, SoC) including one or several CPU subsystems to execute software and sophisticated interconnect in addition to specific hardware subsystems. Mastering the design of these embedded systems is a challenge for both system and semiconductor houses that used to apply only software strategy or only hardware strategy. This paper analyzes this evolution and defines long term roadmaps for embedded system design.

Abstract- This paper presents a full System-on-Chip (SoC) design flow from system specification to RT-level. A new approach to obtain a full path to implementation for SoC design is proposed. This approach combines architecture design space exploration using the VCC design environment and system synthesis using the ROSES design flow, allowing a true and complete system level design flow. The experiment with a VDSL application shows a significant reduction of design time. I.

This paper presents a high-level component-based methodology and design environment for application-specific multicore SoC architectures. Component-based design provides primitives to build complex architectures from basic components. This bottom-up approach allows design-architects to explore efficient custom solutions with best performances. This paper presents a high-level component-based methodology and design environment for application-specific multicore SoC architectures. The system specifications are represented as a virtual architecture described in a SystemC-like model and annotated with a set of configuration parameters. Our component-based design environment provides automatic wrapper-generation tools able to synthesize hardware interfaces, device drivers, and operating systems that implement a high-level interconnect API. This approach, experimented over a VDSL system, shows a drastic design time reduction without any significant efficiency loss in the final circuit.

Embedded memory plays a critical role to improve performances of systems-on-chip (SoC). In this paper, we present a new methodology for embedded memory design in the case of application specific multiprocessor system-on-chip. This approach facilitates the integration of standard memory components. The concept of memory wrapper allows automatic adaptation of physical memory interfaces to a communication network that may have a different number of access ports. We give also a generic architecture to produce this memory wrapper. This approach has successfully been applied on a low-level image processing application.

The ITRS Technology Roadmap recent revision has shown again an acceleration of the Very Deep Submicron process availability with design capabilities forecasted in hundred millions of gates per square centimeter in 2010. This will again raise the question on how to cope with such complexities and functionalities (A-D,HWSW, MEMS... ) in EDA solutions. In this panel will be discussed what are the main priorities in EDA as seen through the applications specificities in USA (ITRS-2001 DESIGN ITWG) and in Europe (The MEDEA EDA Roadmap). The panelists will present the strategies in their respective fields of interest, resulting from their working groups conclusions. They will underline the breakthroughs and potential developments of solutions and the milestones to reduce design times and increase design quality. The focus will be on application driven solutions, mostly in the SoC domains (covering both hardware, embedded and application software).

To enable fast and accurate evaluation of HW/SW implementation choices of on-chip communication, we present a method to automatically generate timed OS simulation models. The method generates the OS simulation models with the simulation environment as a virtual processor Since the generated OS simulation models use final OS code, the presented method can mitigate the OS code equivalence problem. The generated model also simulates different types of processor exceptions. This approach provides two orders of magnitude higher simulation speedup compared to the simulation using instruction set simulators for SW simulation.

This paper addresses performance estimation and architecture exploration issues within the context of hardware/software codesign. We introduce a new methodology to rapidly explore the large design space encountered in hardware/software systems. The proposed methodology is based on a fast and accurate estimation approach. This estimation approach takes advantage of both system and RT levels of abstraction, and combines both static and dynamic analysis techniques, in order to obtain the best trade-off between speed and accuracy. It has been implemented as an extension to a hardware/software codesign flow to enable the exploration of a large number of multiprocessor architecture solutions from the very start of the design process. The effectiveness of the proposed methodology is illustrated by a significant application example. Experimental results indicate strong advantages of the proposed methodology.

In this paper, we present a cosimulation environment that provides modularity, scalability, and flexibility in cosimulation of SoC designs with heterogeneous multi-processor target architectures. Our cosimulation environment is based on an object-oriented simulation environment, SystemC. Exploiting the object orientation in SystemC representation, we achieve modularity and scalability of cosimulation by developing modular cosimulation interfaces. The object orientation also enables mixed-level cosimulation to be easily implemented thereby the designer can have flexibility in trade off between simulation performance and accuracy. Experiments with an IS-95 CDMA cellular phone system design show the effectiveness of the cosimulation environment.

The design starting point for current embedded systems design is getting higher and higher on the abstraction level scale in order to meet the challenge of the increasing design gap. Up till now the state-of-the-art tools and methods have used as a highest abstraction of communication the send-receive over a channel, e.g. as in SDL and COSSAP. We introduce a novel higher level communication mechanism for system-level specification which has features supporting object-oriented descriptions and client-server type communication modelling as in CORBA. The communication primitives have been implemented as extensions to System-C, and simulation experiments have been performed.

We present a design flow for the generation of application-specific multiprocessor architectures. In the flow, architectural parameters are first extracted from a high-level system specification. Parameters are used to instantiate architectural components, such as processors, memory modules and communication networks. The flow includes the automatic generation of communication coprocessor that adapts the processor to the communication network in an application-specific way. Experiments with two system examples show the effectiveness of the presented design flow.

In this paper, we present a novel approach for the design of application specific multiprocessor systems-on chip. Our approach is based on a generic architecture model which is used as a template throughout the design process. The key characteristics of this model are its great modularity, flexibility and scalability which make it reusable for a large class of applications. In addition, it allows one accelerate the design cycle. This paper focuses on the definition of the architecture model and the systematic design flow that can be automated. The feasibility and effectiveness of this approach are illustrated by two significant demonstration examples.

We propose a method of automatic generation of application specific operating systems (OS's) and automatic targeting of application software. OS generation starts from a very small bur yet flexible OS kernel. OS services, which are specific to the application and deduced from dependencies between services, are added to the kernel to construct the whole OS. Communication and synchronization functions in the application code are adapted to the generated OS. As a preliminary experiment, we applied the proposed method to a system example called token ring system.

In this paper we propose a method of mixed-level cosimulation that enables gradual refinement of SoC communication from protocol-neutral communication to protocol-fixed communication. For fine granularity in refinement, the method enables the designer to perform channel refinement and module refinement. Thus, the designer can perform more extensive design space exploration in communication refinement. We show the effectiveness of the proposed method in a case study of communication refinement is an IS-95 CDMA cellular phone system design.

The elevation of design description abstractions is a well accepted technique for handling the complexity and shortening the design time of modern embedded systems. It is shown that abstractions for communication are as important as for behaviour for specification and system level abstractions, and an extension on a novel higher level communication mechanism which has features for supporting the description of complex aggregate associations between objects in specifications such as UML is investigated. The communication primitives have been implemented as extensions to SystemC, and a comprehensive example from a UML specification through functional specification down to an executable SystemC description is included.

Software (SW) parts become crucial in embedded systems. Operating systems (OSs) are often used to handle SW concurrency and communication. We propose a method of automatic generation of application-specific OSs and automatic targeting of application SW. OS generation starts from a very small, but yet flexible OS kernel. OS services, which are specific to the application and deduced from dependencies created by the system specification, are added to the kernel to construct the whole OS. Communication and synchronization functions in the application code are adapted to the generated OS. As experiments, we applied the proposed method to two system examples: a token-ring system and a very high data-rate digital subscriber line framer.

The use of several languages in the design of embedded systems is very convenient for application development and optimization but it can become an obstacle on the way to higher design productivity. This paper explains solutions and future trends.

Summary form only given. With the rising complexity of electronic systems, containing more and more both hardware and software parts, it becomes necessary to simulate simultaneously hardware and software parts at whatever abstraction level. These simulation techniques, called co-simulation, require fast and flexible simulators. In this paper we introduce the elaboration of a microcontroller simulator for an accurate hardware/software co-simulation at the clock-cycle level. It is our goal to have a simulator which is fast enough to simulate a few minutes of real time execution within a reasonable lapse of time. To be more precise, we deal here with the realization of a simulator for the ST10 microcontroller and its integration into a co-simulation environment.

This paper illustrates an approach to design and validation of heterogeneous systems. The emphasis is placed on devices which incorporate MEMS parts in either a single mixed-technology (CMOS + micromachining) SOC device, or alternatively as a hybrid system with the MEMS part in a separate chip. The design flow is general, and it is illustrated for the case of applications embedding CMOS sensors. In particular, applications based on finger-print recognition are considered since a rich variety of sensors and data processing algorithms can be considered. A high level multi-language/multi-engine approach is used for system specification and co-simulation. This also allows for an initial high-level architecture exploration, according to performance and cost requirements imposed by the target application. Thermal simulation of the overall device, including packaging, is also considered since this can have a significant impact in sensor performance. From the selected system specification, the actual architecture is finally generated via a multi-language co-design approach which can result in both hardware and software parts. The hardware parts are composed of available IP cores. For the case of a single chip implementation, the most important issue of embedded-core-based testing is briefly considered, and current techniques are adapted for testing the embedded cores in the SOC devices discussed.

Although very popular and largely wanted, behavioral synthesis was never widely accepted by designers. This paper analyzes the reasons for this failure and introduces a new generation of behavioral synthesis tools with more practical synthesis schemes. The main breakthrough of this new generation is the redefinition of the behavioral synthesis flow to better profit from the power of modern RTL and FSM synthesis. The synthesis results for two large design examples: a 2-million transistors ATM shaper and a motion estimator for a video codec (H261 standard) are shown. They illustrate the effectiveness of this new approach when compared with RT-level design methodologies.

The complexity of modern embedded systems requires the cooperation of several teams belonging to different cultures and using different languages as well as the reuse of software, hardware and communication IP modules at the early design steps. The key issue for the design of such systems is the overall system validation and the synthesis of the communication between the different subsystems. In this paper we focus on the problem of multi-level communication synthesis and show the results of the application of this methodology on an example. Designers get feedback at all design steps via the cosimulation engine that permits fast evaluation.

This paper describes the experience and the lessons learned during the design of an ATM traffic shaper circuit using behavioral synthesis. The experiment is based on the comparison of the results of two parallel design flows starting from the same specification. The first used a classical design method based on RTL synthesis. The second design flow is based on behavioral synthesis. The experiment has shown that behavioral synthesis is able to produce efficient design in terms of gate count and timing while bringing a threefold reduction in design effort when compared to the RTL design methodology.

The design of large systems, like a mobile telecommunication terminal or the electronic parts of an airplane or a car, may require the participation of several groups belonging to different companies and using different design methods, languages and tools. The concept of multi-language specification aims at coordinating different cultures through the unification of the languages, formalism and notations. This hot topic discusses the main issues and approaches to multi-language design. Two research directions are currently being explored by the EDA community. The first is based on the computation models underlying the languages while the second deals with the specification languages themselves.

This paper deals with integrating an interactive simulator within a behavioral synthesis tool, thereby allowing concurrent synthesis and simulation. The resulting environment provides a cycle based simulation of a behavioral module under synthesis. The simulator and the behavioral synthesis are based on a single model that allows one to link the behavioral description and the architecture produced by synthesis. The basic simulation-synthesis model is extended in order to allow for concurrent architectural simulation of several modules under synthesis. This paper also discusses an implementation of this concept resulting in a simulator, called AMIS. This tool assists the designer for understanding the results of behavioral synthesis and for architecture exploration. It may also be used to debug the behavioral specification.

This paper introduces one way to integrate an interactive simulator within a behavioral synthesis tool, thereby allowing concurrent synthesis and simulation. Such a simulator performs dynamic analysis and time evaluation. This paper also discusses an implementation of this concept resulting in a simulator, called AMIS. This tool assists the designer for understanding the results of behavioral synthesis and for architecture exploration.

This paper outlines a case study at SGS-Thomson Microelectronicson the development of a firmware development environment in co-operationwith Thomson Consumer Electronics Components. Theenviornment is for an embedded processor used for audiodecompression algorithms including: MPEG2, Dolby AC-3 Surround,and Dolby Pro-logic. The enabling component of the firmwareenvironment is a retargetable compiler which maps high-levelalgorithms onto the embedded processor. Although compilation is thecritical technology, this experience has shown that it is insufficient andthat other supporting design tools are also important. For this project,that environment includes an instruction-set simulator, a source-leveldebugger, a custom linker, and a compiler validation strategy. Themethodologies are outlined in this paper with an emphasis on thelessons learned in this hardware-software team development.

This paper presents the underlying methodology of Cosmos, an interactive approach for hardware/software co-design capable of handling multiprocessor systems and distributed architectures. The approach covers the co-design process through a set of user guided transformations allowing semi-automatic partitioning. The transformations are based on a powerful set of primitives for functional partitioning, structural reorganization and communication transformation. It leads to a fast transformation of a system-level specification into an architecture with a short design time and fast exploration of design space. The application of this approach is illustrated using a design example starting from a system-level specification given in SDL to a distributed hardware/software architecture described in C/VHDL. We show that the use of transformational approach allows: 1) application of the expertise of the designer during partitioning; 2) the user to understand the results of the co-design process; 3) the process to take into account partial existing solutions; 4) large design space exploration; and 5) the designer to start from a very high-level specification language of the system to be designed.

The aim of this paper is to present a communication synthesis approach stated as an allocation problem. In the proposed approach, communication synthesis allows to transform a system composed of processes that communicate via high-level primitives through abstract channels into a set of processes executed by interconnected processors that communicate via signals and share communication control. The proposed communication synthesis approach deals with both protocol selection and interface generation and is based on binding/allocation of communication units. This approach allows a wide design space exploration through automatic selection of communication protocols. We present a new algorithm that performs binding/allocation of communication units. This algorithm makes use of a cost function to evaluate different allocation alternatives. We illustrate through an example the usefulness of the algorithm for allocating automatically different protocols within the same application system.

This paper presents the design of a Videophone Coder-Decoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (complex communication protocol) with a Data Flow Dominated part (high throughput computations) makes this circuit difficult to be synthesized by a single HLS tool. The combination of two HLS tools for the high-level design of this operator required the definition of a sophisticated design flow allowing mixed-level and multi-language simulations. When compared to design starting from RTL specifications, HLS induces only a negligible area overhead of 5%, and provides gain in description length (divided by 5), design time and flexibility.

The advent of parallel executing address calculation units (ACUs) in digital signal processor (DSP) and application specific instruction-set processor (ASIP) architectures has made a strong impact on an application's ability to efficiently access memories. Unfortunately, successful compiler techniques which map high-level language data constructs to the addressing units of the architecture have lagged far behind. Since access to data is often the most demanding task in DSP, this mapping can be the most crucial function of the compiler. This paper introduces a new retargetable approach and prototype tool for the analysis of array references and traversals for efficient use of ACUs. The ArrSyn utility is designed to be used either as an enhancement to an existing dedicated compiler or as an aid for architecture exploration.

This paper presents a distributed hardware/software cosimulation environment for heterogeneous systems prototyping applied to an industrial application. The environment provides following features: distributed Hw/Sw cosimulation, automatic Hw/Sw interface generation, Hw elements can be described at different levels of abstraction and generic/specific Sw debuggers can be used. Starting from a brief description of the interface of the interconnected modules the tool automatically produces the link between Hw and Sw parts. In addition, the environment is very easy to use, even for complex systems that may include several Sw (C) modules and several Hw (VHDL) modules running in parallel. Applied to a large industrial multi-processor system, this method appeared reliable and efficient, providing important benefits in hardware-software codesign: better design environment and reduced time to validate.

The paper presents a methodology and an experiment for rapid avionics prototyping using the STATEMATE environment. The methodology is based on SA-RT structured analysis principles. It shows first the context of STATEMATE use in the current avionics development process. Therefore, it sets up some key steps and use recommendations in order to enhance the modeling quality The experiment deals with the re-design of all existing avionics system that is part of the AIRBUS A340 on-board systems family. It highlights the STATEMATE modeling, validation and rapid prototyping facilities. Results and perspectives are also outlined.

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This paper presents a method for modeling and synthesizing mixed HW/SW systems. The proposed method starts from a full system-level specification. Systems are modeled in a synthesis-oriented manner by means of an extended finite state machine model. System-level synthesis is composed of three tasks: partitioning systems into inter-dependent sub-systems, inter-subsystem communication synthesis and architecture mapping onto a flexible architecture platform which includes both hardware and software components. The overall method is illustrated with an example.>

This paper deals with using architectural synthesis and structured design methodology in order to accelerate the design process. Such task will be achieved using AMICAL, an architectural synthesis tool allowing the design of complex systems. The design starts with a behavioral description and a library of functional units. The library may include standard components and/or complex sub-systems that may be designed using other design tools and methodologies or using AMICAL itself. A design example, namely a PID (Proportional Integral Derivative) is used to illustrate the methodology. The synthesis of the PID is done using several functional unit libraries. The most interesting synthesis results are those obtained on having a sub-system (fixed-point unit) designed using AMICAL, and re-used as a functional unit for the synthesis of the full design.>

The authors describe a design-for-testability strategy for the SYCO control section compiler (CPC). The SYCO CPC translates high-level descriptions into mask-level specification for hierarchical control sections, which are composed of a stack of control section slices, each one organized around a programmable logic array. The proposed design-for-testability scheme is called UBIST (unified built-in self-test) and ensures a high quality for all tests needed for integrated circuits (i.e. online and offline tests). The authors elucidate the concept of UBIST and show how to modify SYCO CPC data structure and its automatic layout synthesizer to generate UBIST control sections automatically and efficiently.>

The SYCO system is a silicon compiler for VLSI circuits specified by algorithms. The SYCO system starts from an algorithmic description and produces a microprocessor-like circuit that realizes the algorithm. It uses a target architecture based on a multiple interpretation level scheme. A large interpreter of a given command language is split into a set of interpreter levels. Each interpreter level breaks down the commands given by the upper level into a set of sub-commands for the lower level. Each interpreter level is implemented by a block of layout called a layout slice. A chip will contain one data path slice and several control section slices. The SYCO system makes use of a set of specialized compilers to produce the layout of the datapath and of the control section slices. These slices are generated to be automatically assembled together. The whole system is written in Le Lisp. It is expected that the SYCO system will give the ability to compile circuits, which have the complexity of the MC68000. The SYCO system is developed in the framework of the SYCOMORE French National Project for CAD of VLSI.