In this paper, we are concerned about the frequency domain noise canceller to decrease the number of calculation for its realization. In order to treat the long delay and multi-reflection impulse responses of room, we propose a new method of Frequency Bin Adaptive Filtering (FBAF). Each frequency bin of the FFT data is fed in an independent Tapped Delay Line (TDL) to be processed by the extended complex LMS algorithm. The computer simulation results indicate that the proposed FBAF method has better performance than a simple frequency domain adaptive filter. Especially, when a long term delay is considered the robustness, fast convergency and stability in performance will be obvious. Another merit of FBAF method is the short delay between input and output of the system as a result of utilization of short length window function. The number of calculation is comparable with the one of frequency domain filter and much less than the one of time domain adaptive filter. So that, it is convenient to realize the FBAF method by using a few chips of DSP.

This paper describes a new 32 kbps ADPCM CODEC which shows high-quality speech coding characteristics and data transmission capability up to 9600 bps. The proposed ADPCM CODEC consists of two coding modes. The first coding mode can code the speech signal and the data transmission signal up to 4800 bps by using the coding algorithm of CCITT recommendation G.721. The second coding algorithm is tuned to handle the 9600 bps modem signal. These two coding modes are automatically switched depending on the input signal to the CODEC. The switching algorithm is based on detection of modem training signal and is found to be highly reliable in practical environments. This algorithm thus provides a means to be compatible with the standard CCITT algorithm for speech and data transmission up to 4800 bps and at the same time be transparent to data transmission at 9600 bps.

This paper proposes an alternative to the passive bus realization of the current CCITT ISDN user-network interface. Our new approach is termed phase aligned passive bus (PAB) scheme. An automatic phase adjusting mechanism using a monitor bit is employed in the terminal equipment. This scheme enables the terminals to operate in complete phase synchronization on a passive bus. The advantages that result from this technique are: 1) Eliminates, in principle, the bus length limitation due to round-trip delay time. If line bit rate of 192 kbit/s is kept, then a practical bus length is about 700 m with no limitation on terminal distribution. 2) Allows various extended bus configurations, such as simple repeatered extention, connection of optical link, and multibranched passive bus. 3) Provides spare bit transmission capability to facilitate intrabus communication and maintenance. As an alternative it keeps the general framework of the current CCITT I-series standard such asB + B + Dchannel structure and LAP-Dprotocol. Experiments realizing long passive buses are shown to confirm the feasibility of the proposed scheme. This concept is also shown to be applicable to a 2-wire full duplex user-network interface, advantageous in the existing office environment, employing time compression transmission.

This paper describes an implementation of a CCITT G.721 compatible 32kbit/s ADPCM codec, using a general-purpose digital signal processor FDSP-3 (MB8764). A single-channel ADPCM codec is realized by two FDSP-3 chips-one for the encoder and the other for the decoder. Meticulous programming techniques are employed to achieve exact computation of the CCITT algorithm exploiting all the available resources of the 16-bit fixed-point DSP. It is shown that the whole codec computation can be accomplished in about 2350 machine cycles. Thus, two FDSP-3 chips operating at 10 MHz machine cycle can handle the whole computation. The paper also covers the comparison of straight fixed-point format and the G.721 realization, and briefly examines the compatibility issue between these two methods.

This paper describes a newly developed CMOS LSI DSP (FDSP3). It has a powerful multiplier, which operates at a rate of 10 M-operations/s, almost twice as fast as the fastest existing LSI DSP's. Some key techniques to attain these high performance characteristics of the DSP are described. Suitable memory capacities of the RAM and ROM were analyzed as a function of the operational capability of the DSP. These were reflected in the design of the FDSP3. To assist in the development of the program, support tools have been developed. A Pascal based cross compiler and an on-line debugging tool are described in some detail.

This paper describes a newly developed CMOS LSI DSP and its application to a 32 Kbps ADPCM CODEC and a 4,800 bps data MODEM. The paper first analizes the required memory capacities of ROM and RAM as a function of arithmatic operation capability of DSP. Based on the results, the LSI DSP is developed, which has a proper amount of memory capacities. It has a multiplier which operates at a rate of 1.4 M operations/s. It is also equipped with a versatile I/O interface circuit which is suitable for multi-processors configuration of a system.

This paper describes a complete hardware implementation of a 24 channel transmultiplexer employing a digital signal processor. The algorithm for the TDM-FDM translation adopted here is a modification of the FFT and digital polyphase method. The modification is mainly directed towards the reduction of roundoff noise, so that the wordlength of the processor can be minimized. In this case, 16 bits for multiplication with double precision accumulation is found to be sufficient to meet the noise requirements as recommended by CCITT G.792. The above modification enables the implementation of the translation algorithm by a 16 bit parallel type digital signal processor. This processor is designed to be firmware controllable and, thus, has a wide range of applications. The entire 24 channel transmultiplexer comprises 1) four signal processors, each handling 12 channels one way translation including signaling; 2) digital interface part to connect to 1.544 Mbit/s PCM system; and 3) codec and Nyquist filter to connect to two 12-channel FDM systems.

This paper describes a fast data processing LSI unit tailored to the digital signal processing (DSP) applications in the field of electrical communications. The results of successful application to the 4800 bit/s modem are also given. The LSI processor discussed here adopts a firmware control scheme to enhance the flexibility and freedom of application and extensively utilizes the pipeline processing technique to attain high speed data handling capability. The various operations encountered in DSP systems are unified into one operation of the typeA \times B + C \rightarrow Dand the LSI processor is designed to continuously perform this operation, while the data to be operated are transferred sequentially into the processor controlled by exterior firmware. The developed LSI handles 8 bit data at the clock frequency of 1.152 MHz and manages 144 K operations per second (6.9 μs cycle time). The LSI is an N-MOS chip containing 1500 gates and packaged in a 40 pin DIP. The automatic equalizer for 4800 bit/s modem was implemented using two of the developed LSI processors and about 4 K ROM and 1 K RAM memory chips. The measurement on this modem gave the error rate of 10-5atS/N = 17.6dB and error free phase jitter allowance of 55° p-p. Application of the LSI processor to digital filters for roll-off spectrum shaping and timing signal extraction is also described.