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Ramesh Peri

dblp:26/3936 · DBLP profile ↗
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8ranked-venue papers
0as first author
2since 2021 · last 2025
0009-0009-4272-4211ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 2 since 2021Software engineering, systems software and programming languages · 4Databases, data management, data science and information retrieval · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Memory systems · 27% Energy-efficient computing · 25% High-performance computing · 12%
Databases, data mining, and information retrieval
1 paper
Graph data management · 100%
Software engineering, system software, and programming languages
1 paper
Concurrent programming · 87% Program analysis · 13%

Topics — the 10 heaviest of 13, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
non-volatile memory
0.922021
Single-node partitioned-memory for huge graph analytics: cost and performance trade-offs · SC 2021
Single Machine Graph Analytics on Massive Datasets Using Intel Optane DC Persistent Memory · Proc. VLDB Endow. 2020
Graph data management
graph analytics
0.512021
Single-node partitioned-memory for huge graph analytics: cost and performance trade-offs · SC 2021
Graph data management › graph analytics
large-scale graph analytics
0.512021
Single-node partitioned-memory for huge graph analytics: cost and performance trade-offs · SC 2021
High-performance computing
large-scale graph processing
0.412020
Single Machine Graph Analytics on Massive Datasets Using Intel Optane DC Persistent Memory · Proc. VLDB Endow. 2020
Storage systems › out-of-core computation
out-of-core graph processing
0.412020
Single Machine Graph Analytics on Massive Datasets Using Intel Optane DC Persistent Memory · Proc. VLDB Endow. 2020
Integrated circuit design
3d integration
0.312025
CORDOBA: Carbon-Efficient Optimization Framework for Computing Systems · HPCA 2025
Parallel and multicore computing › parallel graph algorithms
shared-memory parallel graph algorithm
0.112020
Single Machine Graph Analytics on Massive Datasets Using Intel Optane DC Persistent Memory · Proc. VLDB Endow. 2020
Concurrent programming › concurrency bug detection
data race detection
0.112011
Demand-driven software race detection using hardware performance counters · ISCA 2011
Concurrent programming › concurrency bug detection › data race detection
dynamic race detection
0.112011
Demand-driven software race detection using hardware performance counters · ISCA 2011
Program analysis
dynamic analysis
0.012011
Demand-driven software race detection using hardware performance counters · ISCA 2011

Methods — techniques the papers use, named apart from their topics

performance evaluation · 1.0partitioned memory · 1.0design space exploration · 0.9hardware performance counters · 0.1
YearPublicationVenuePosition
2025 CORDOBA: Carbon-Efficient Optimization Framework for Computing Systems
abstract
The world’s push toward an environmentally sustainable society is highly dependent on the semiconductor industry. Despite existing carbon modeling efforts to quantify carbon footprint of computing systems, optimizing carbon footprint in large design spaces-while also considering trade-offs in power, performance, and area-is especially challenging. To address this need, we present CORDOBA, a carbon-aware optimization framework that optimizes carbon efficiency. We quantify carbon efficiency using the total Carbon Delay Product metric (tCDP): the product of total carbon and application execution time. We justify why tCDP is an effective metric for quantifying carbon efficiency. We use CORDOBA to explore the large design space for carbonefficient specialized hardware, and identify distinct carbonefficient optimal designs across operational use (eliminating up to $\mathbf{9 8 \%}$ of the design space) despite uncertainty in carbon footprint parameters. We quantify opportunities to improve tCDP for real system case studies: (a) optimizing hardware provisioning from 8 to 4 cores in real system CPUs improves tCDP by $1.25 \times$; and (b) leveraging advanced three-dimensional (3D) integration techniques (3D stacking of separately-fabricated logic and memory chips) improves tCDP by $6.9 \times$ versus conventional systems.
Mariam Elgamal, Doug Carmean, Elnaz Ansari, Okay Zed, Ramesh Peri, Srilatha Manne, Udit Gupta 0001, Gu-Yeon Wei, David Brooks 0001, Gage Hills, Carole-Jean Wu
HPCA5
2021 Single-node partitioned-memory for huge graph analytics: cost and performance trade-offs
abstract
Because of cost, non-volatile memory NVDIMMs such as Intel Optane are attractive in single-node big-memory systems. We evaluate performance and cost trade-offs when using Optane as volatile memory for huge-graph analytics. We study two scalable graph applications with different work locality, access patterns, and parallelism. We evaluate single and partitioned address spaces---Memory and AppDirect modes---and compare with distributed executions on GPU-accelerated and CPU-based supercomputers.
Nathan R. Tallent, Marco Minutoli, Mahantesh Halappanavar, Ramesh Peri, Anantharaman Kalyanaraman
SC5
2020 Single Machine Graph Analytics on Massive Datasets Using Intel Optane DC Persistent Memory
abstract
Intel Optane DC Persistent Memory (Optane PMM) is a new kind of byte-addressable memory with higher density and lower cost than DRAM. This enables the design of affordable systems that support up to 6TB of randomly accessible memory. In this paper, we present key runtime and algorithmic principles to consider when performing graph analytics on extreme-scale graphs on Optane PMM and highlight principles that can apply to graph analytics on all large-memory platforms. To demonstrate the importance of these principles, we evaluate four existing shared-memory graph frameworks and one out-of-core graph framework on large real-world graphs using a machine with 6TB of Optane PMM. Our results show that frameworks using the runtime and algorithmic principles advocated in this paper (i) perform significantly better than the others and (ii) are competitive with graph analytics frameworks running on production clusters.
Gurbinder Gill, Roshan Dathathri, Loc Hoang, Ramesh Peri, Keshav Pingali
Proc. VLDB Endow.4
2015 Mosaic: cross-platform user-interaction record and replay for the fragmented android ecosystem
abstract
In contrast to traditional computing systems, such as desktops and servers, that are programmed to perform “compute-bound” and “run-to-completion” tasks, mobile applications are designed for user interactivity. Factoring user interactivity into computer system design and evaluation is important, yet possesses many challenges. In particular, systematically studying interactive mobile applications across the diverse set of mobile devices available today is difficult due to the mobile device fragmentation problem. At the time of writing, there are 18,796 distinct Android mobile devices on the market and will only continue to increase in the future. Differences in screen sizes, resolutions and operating systems impose different interactivity requirements, making it difficult to uniformly study these systems. We present Mosaic, a cross-platform, timing-accurate record and replay tool for Android-based mobile devices. Mosaic overcomes device fragmentation through a novel virtual screen abstraction. User interactions are translated from a physical device into a platform-agnostic intermediate representation before translation to a target system. The intermediate representation is human-readable, which allows Mosaic users to modify previously recorded traces or even synthesize their own user interactive sessions from scratch. We demonstrate that Mosaic allows user interaction traces to be recorded on emulators, smartphones, tablets, and development boards and replayed on other devices. Using Mosaic we were able to replay 45 different Google Play applications across multiple devices, and also show that we can perform cross-platform performance comparisons between two different processors under identical user interactions.
Matthew Halpern, Yuhao Zhu 0001, Ramesh Peri, Vijay Janapa Reddi
ISPASS3
2011 Demand-driven software race detection using hardware performance counters
abstract
Dynamic data race detectors are an important mechanism for creating robust parallel programs. Software race detectors instrument the program under test, observe each memory access, and watch for inter-thread data sharing that could lead to concurrency errors. While this method of bug hunting can find races that are normally difficult to observe, it also suffers from high runtime overheads. It is not uncommon for commercial race detectors to experience 300x slowdowns, limiting their usage.
Joseph L. Greathouse, Matthew I. Frank, Ramesh Peri, Todd M. Austin
ISCA4
2009 Chainsaw: Using Binary Matching for Relative Instruction Mix Comparison
abstract
With advances in hardware, instruction set architectures are undergoing continual evolution. As a result, compilers are under constant pressure to adapt and take full advantage of available features. However, current techniques for evaluating relative compiler performance only compare profiles at the application level, ignoring relative performance differences at finer granularities. To ensure that new features are put to good use, a more rigorous approach is necessary. A fundamental step in tuning compiler performance is identifying the specific examples that can be improved. To solve this problem, we present a compiler-independent binary matching technique to compare executions of differently compiled programs and identify intervals where the behavior can be meaningfully compared. Matched intervals can be automatically analyzed to identify anomalous segments of execution where one version performs significantly differently versus another. We present case studies using Chainsaw to identify significant performance anomalies between differently compiled codes.
Tipp Moseley, Dirk Grunwald, Ramesh Peri
PACT3
2009 OptiScope: Performance Accountability for Optimizing Compilers
abstract
Compilers employ many aggressive code transformations to achieve highly optimized code. However, because of complex target architectures and unpredictable optimization interactions, these transformations may not always be beneficial. Current analysis methods measure performance at the application level and ignore optimization effects at the function and loop level. To better measure and understand these effects, we present OptiScope, a compiler independent tool to identify performance opportunities by comparing programs built with different compilers or optimization flags. The analysis includes hundreds of different metrics and uses a novel loop correlation technique for binary programs (produced from the same source by different compilers) to isolate measurements to specific regions. We present several case studies using OptiScope to identify key differences between different compiler suites, versions, and target architectures. The examples demonstrate performance improvement opportunities between 32.5% to 893% on select regions of SPEC 2006 benchmarks.
Tipp Moseley, Dirk Grunwald, Ramesh Peri
CGO3
2007 Shadow Profiling: Hiding Instrumentation Costs with Parallelism
abstract
In profiling, a tradeoff exists between information and overhead. For example, hardware-sampling profilers incur negligible overhead, but the information they collect is consequently very coarse. Other profilers use instrumentation tools to gather temporal traces such as path profiles and hot memory streams, but they have high overhead. Runtime and feedback-directed compilation systems need detailed information to aggressively optimize, but the cost of gathering profiles can outweigh the benefits. Shadow profiling is a novel method for sampling long traces of instrumented code in parallel with normal execution, taking advantage of the trend of increasing numbers of cores. Each instrumented sample can be many millions of instructions in length. The primary goal is to incur negligible overhead, yet attain profile information that is nearly as accurate as a perfect profile. The profiler requires no modifications to the operating system or hardware, and is tunable to allow for greater coverage or lower overhead. We evaluate the performance and accuracy of this new profiling technique for two common types of instrumentation-based profiles: interprocedural path profiling and value profiling. Overall, profiles collected using the shadow profiling framework are 94% accurate versus perfect value profiles, while incurring less than 1% overhead. Consequently, this technique increases the viability of dynamic and continuous optimization systems by hiding the high overhead of instrumentation and enabling the online collection of many types of profiles that were previously too costly
Tipp Moseley, Alex Shye, Vijay Janapa Reddi, Dirk Grunwald, Ramesh Peri
CGO5