Syed Zahoor Hassan

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4ranked-venue papers

4as first author

0since 2021 · last 1986

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Electronic design automation · 90% Integrated circuit design · 10%

Topics — the 5 heaviest of 5, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Electronic design automation hardware verification and test	1	1984	Signature Testing of Sequential Machines · IEEE Trans. Computers 1984
Electronic design automation › hardware verification and test sequential circuit testing	1	1984	Signature Testing of Sequential Machines · IEEE Trans. Computers 1984
Integrated circuit design digital circuit design	1	1984	Signature Testing of Sequential Machines · IEEE Trans. Computers 1984
Electronic design automation › logic synthesis programmable logic array	1	1984	Signature Testing of Sequential Machines · IEEE Trans. Computers 1984
Electronic design automation › hardware verification and test › test response compaction signature analysis	1	1984	Signature Testing of Sequential Machines · IEEE Trans. Computers 1984

Year	Publication	Venue	Position
1986	An Efficient Self-Test Structure for Sequential Machines Syed Zahoor Hassan	ITC	1
1984	Pseudo-Exhaustive Testing of Sequential Machines Using Signature Analysis Syed Zahoor Hassan, Edward J. McCluskey	ITC	1
1984	Signature Testing of Sequential Machines abstract A new approach to the testing of sequential machines is presented which employs signature analysis. In the conventional scheme of testing sequential finite state machines, distinguishing and transfer sequences are used. For the purposes of testing sequential machines by signature analysis, a signature distinguishing sequence is defined. An algorithm for augmenting a sequential machine by introducing an extra input is presented. This yields a sequential machine that has a signature distinguishing sequence. The additional cost in terms of the chip area for a programmable logic array (PLA) implementation is calculated. Syed Zahoor Hassan	IEEE Trans. Computers	1
1983	Signature Testing of Sequential Machines Syed Zahoor Hassan	ITC	1