Transaction-level modeling --- originally used decades ago in the development of telecommunications network architecture --- is now widely used in SoC design. Why? Because the modern SoC is now so complex that systematic modeling and analysis are required to devise the optimal chip architecture. The architectural model is the essential platform that kick-starts two other key tasks --- verification testbench development and software development. In addition, the interoperability imperatives of SoC design and verification, IP reuse, software development, and system evaluation and integration have driven the replacement of proprietary transaction-level modeling methodologies by a TLM standard that leverages the power of SystemC. The standard --- devised by the Open SystemC Initiative (OSCI) in collaboration with the Open Core Protocol International Partnership (OCP-IP) --- covers the multiple levels of abstraction required for all of the foregoing tasks.

The need to partition computation across multiple programmable devices in array architecture CCMs leads to performance bottlenecks in data flow through the computer and wiring delays between adjacent devices. However, significant improvements in FPGA capacities have brought one to a threshold where direct inter-chip connections are not required because an entire algorithm can be implemented on a single device for important problems in areas such as image processing. One can now implement architectures that are similar to today's parallel computers in which interprocessor communication is done through shared memory or dedicated communication hardware. The benefits of this approach are system-wide scalability and flexibility. The authors illustrate this new style of CCM with examples from image processing, in particular a novel FPGA implementation of block motion estimation (as for MPEG encoding). Based on the lessons learned from these specific examples, they generalize and speculate on implications for new CCM architectures.

The authors propose a novel specification for tightly constrained processing elements based on recognizing concurrent sequences of data flow. This specification has several benefits, notably it allows a very concise representation of complex internal semantics and interface protocols. Particular advantages exist with specifying timing constraints and performance cost functions for control dominated applications. The specification can be made canonical and leads to an interesting formulation of the scheduling problem.>