This paper presents a study of the implication based functional constraint extraction techniques to generate pseudo functional scan tests. Novel algorithms to extract pair-wise and multi-node constraints as Boolean expressions on arbitrary gates in the design are presented. Its impact on reducing the overkill in testing was analyzed, and report the trade-offs in coverage and scan-loads for a number of fault models. In the case of path-delay fault model, it was shown that the longest paths contribute most to the over-testing problem, raising the question about scan testing of the longest paths. Finally, the evaluation of the functional constraints on large industrial circuits show that the proposed constraint generation algorithm generate a powerful set of constraints most of which are not captured in the constraints extracted by designers for design-verification purposes

This paper presents two low-cost fault-independent techniques that can be used to identify significantly more untestable faults than could be identified by earlier fault-independent techniques. A new theorem and an efficient implementation of the theorem for the purpose of identifying sequentially untestable faults are presented first. Unlike the single-fault theorem where the stuck-at fault is injected exclusively in the last time frame of the k-frame unrolled circuit, this theorem enables a fault injection in any time frame within the unrolled sequential circuit. To efficiently apply the authors' concept to untestable fault identification, sequential implications are used to extend the unobservability propagation of gates to multiple time frames during single-line conflict analysis. Then, a new technique called "maximizing local impossibilities" is proposed. This technique efficiently identifies multiple-node conflicting assignments by analyzing logical relationships local to Boolean gates in the circuit. Using this new concept in conjunction with a powerful implication engine enables identification of many more untestable faults that were missed by the single-line conflict-based approach. Since this approach concentrates on identifying conflicting combinations locally around each Boolean gate in the circuit, its complexity is linear in the size of the circuit. The application of these two proposed techniques to the International Symposium on Circuits and Systems (ISCAS) 1985 and ISCAS 1989 Sequential Benchmark Circuits showed a significant increase in the number of faults identified as untestable, at practically no overhead in both the memory and the execution time

The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across latches results in signals which propagate across multiple clock cycles along paths with multiple latches. These paths need to be tested for delay failures to ensure reliability of performance. However, many of these multi-cycle paths can be untestable and significant computational effort is wasted in targeting such paths during test generation and fault grading. To save this computational effort, a-priori identification of untestable multicycle paths is desired. We address this issue in our paper through a novel and unique framework: unlike traditional techniques, which focus only on single-cycle path delay faults (for flip-flop based designs with single clock), our framework efficiently identifies untestable multi-cycle path delay faults (Mpdfs) in latch-based designs with multiple clocks. We use a novel graphical representation and sequential implications to identify non-robustly untestable M-pdfs through a three-step methodology. Results for industrial designs demonstrate the effectiveness and scalability of our framework.

In this paper, we propose novel low-cost methods that combine static logic implications and binary resolution to significantly increase the number of non-trivial signal relations learned from the circuit. The proposed method first applies resolution techniques to learn new static single-node implications and then uses them to learn powerful multi-node implications. All the newly learned relations help in extracting more necessary assignments for a given fault, potentially increasing the chance for a conflict to occur among the necessary assignments. Experimental results on ISCAS89 and ITC99 benchmarks show that our method can identify significantly more untestable faults compared to existing non branch-and-bound based techniques.

In this paper, we make two major contributions: First, to enhance Boolean learning, we propose a new class of logic implications called extended forward implications. Using a novel concept called implication-frontier, extended forward implications efficiently capture those nontrivial relationships which previous techniques failed to identify. Secondly, we introduce the concept of dual recurrence relations in sequential circuits, and propose a new theorem which uses this concept to quickly identify sequentially untestable faults. Our tool based on the proposed extended forward implications and the new theorem was applied to identify untestable faults in benchmark circuits. Significantly more untestable faults than reported by earlier techniques, low memory overhead and low computational complexity are the noteworthy features of our tool.

This work presents a novel technique to identify functionally untestable transition faults in latch based designs with multiple clock domains, bringing to light unaddressed issues related to untestable fault identification in such design environments. We also introduce and provide a solution to a new variant of un-testability analysis wherein "architectural constraints'' are absorbed during the analysis. We give our tool the capability of handling transition faults resulting from defects of varying sizes, and evaluate our tool for various industrial circuits. The proposed algorithm is compared with a state-of-the-art sequential ATPG tool, and our method has shown much better performance both in the context of scan ATPG and functional test development. Results indicate that the proposed technique identifies considerably more untestable transition faults than those that can be deduced from the knowledge of untestable stuck-at faults. Additional insights from our results point to a greater need to eliminate untestable transition faults as compared to stuck-at faults, for more efficient test pattern generation and accurate coverage computation.

This paper presents a novel, low cost technique based on implications to identify untestable bridging faults in sequential circuits. Sequential symbolic simulation is first performed, as a preprocessing step, to identify nets which are uncontrollable to a specific logic value. Then, an implication-based analysis is carried out for each fault to determine if a particular fault is testable or not. We also use information about the untestable stuck-at faults to filter out some bridges early in the analysis process. The application of our technique to ISCAS '89 sequential benchmark circuits and a few industrial circuits showed that a large number of untestable bridges could be identified at a low cost, both in terms of memory and execution time.