Using multiple power domains is a common technique to achieve significant power savings in modern designs. However, providing power to cross-domain cells is challenging at advanced technology nodes, due to strict IR drop constraints and competition for routing resources between secondary power routing and signal routing. Despite its importance, this issue has received limited attention in recent literature. In this paper, we propose a detailed placement method that accounts for secondary power routing. Our approach employs an integer linear programming (ILP) model, complemented by targeted adjustments to the placement of cross-domain cells, to optimize the efficiency of secondary power routing. We validate our results with commercial design tools, showing that our approach effectively improves secondary power routing performance by reducing the wirelength of the secondary power distribution network (PDN) and decreasing violations due to secondary PDN constraints.

In advanced semiconductor processes, the dramatic shrink of layout features has made a significant impact on circuit delay and electromigration (EM). Recently, meshed stack vias (MSVs) have been proposed as a solution to improve circuit timing and signal integrity, each of which is a multi-layer mesh structure composed of parallel metal shapes and vias. Due to the introduced MSV rules and more and more complicated design rules, MSV design becomes a very challenging problem, while no previous work has addressed this issue. In this paper, we propose the first work of MSV design by developing two different methods: an integer linear programming (ILP)-based and a dynamic programming (DP)-based methods. Unlike most previous works devoting themselves to formulating sophisticated constraints for each complicated design rule, we propose an automatic constraint generation (ACG) framework to iteratively resolve design rule violations (DRVs) without any effort in understanding all design rules, which contributes to a general MSV design methodology applicable to different technology nodes. Experimental results show that both the ILP-based and DP-based approaches can averagely achieve 92% MSV insertion rate for a set of industrial benchmarks. In addition, by adopting the proposed ACG framework, 100% MSV insertion rate can be achieved without causing any DRV.

With the feature size shrinking down to 7 nm and beyond, the impact of wire resistance is significantly growing, and the circuit delay incurred by metal wires is noticeably raising. To address this issue, a new technique called via pillar insertion is developed. However, the poor success rate of the via pillar insertion process immediately becomes an important problem. In this paper, we explore the causes of via pillar insertion failures by experiments on the ISPD 2015 benchmarks, which are embedded with a real industrial cell library. The results show that the reasons for the low success rate may be due to track misalignment, power and ground stripe overlapping, and insufficient margin area. Therefore, we propose the first detailed placement flow which is aware of via pillars to maximize the success rate of via pillar insertion. In the proposed flow, we first filter out infeasible cell rows and then move the via pillar-inserting cells to their eligible positions. Next, we adopt a two-stage legalization method with high flexibility on cell ordering based on a dynamic programming-based detailed placement algorithm. Finally, we improve congested rows with a global moving process. Experiment results show that our algorithm improves the insertion rates by 54-58%, and achieves over 99% insertion rate on average.