Quantum Error Correction (QEC) is the corner-stone of practical Fault-Tolerant Quantum Computing (FTQC), but incurs enormous resource overheads. Circuits must decompose into Clifford +T gates, and the non-transversal T gates demand costly magic-state distillation. As circuit complexity grows, sequential T-gate layers (” T-depth”) increase, amplifying the spatiotemporal overhead of QEC. Optimizing T-depth is NP-hard, and existing greedy or brute-force strategies are either inefficient or computationally prohibitive. We frame T-depth reduction as a search optimization problem and present a Genetic Algorithm (GA) framework that approximates optimal layer-merge patterns across the non-convex search space. We introduce a mathematical formulation of the circuit expansion for systematic layer reordering and a greedy initial merge-pair selection, accelerating the convergence and enhancing the solution quality. In our benchmark with $\mathbf{\sim 9 0 - 1 0 0}$ qubits, our method reduces T-depth by 79.23% and overall T-count by 41.86%. Compared to the standard reversible circuit benchmarks, we achieve a $\sim 2.58 \times$ average improvement in T-depth over the state-of-the-art methods, demonstrating its viability for near-term FTQC.

Spiking Neural Networks (SNNs) are inspired by the event-driven and temporally sparse nature of biological neurons, enabling deployment in in-sensor computing systems. The sensing and computation being tightly coupled in the in-sensor devices help in low-latency and energy-efficient data processing. This paradigm introduces a novel security front, exposing vulnerabilities in both neuromorphic hardware and the temporally sparse spike encodings to a variety of emerging attack modalities. This survey offers a comprehensive examination of the security and robustness landscape for SNNs deployed in in-sensor computing environments. It begins by outlining the architectural and algorithmic characteristics that define in-sensor SNN pipelines, with particular focus on temporal coding, asynchronous processing, and hardware constraints. We then review pertinent threat models, including spike-level adversarial perturbations, sensor spoofing, electromagnetic interference, fault injection, and timing-based privacy leakage, considering both white-box and black-box attack scenarios that exploit spatiotemporal vulnerabilities. Existing defense mechanisms, spanning noise shaping, homeostatic control, adversarial training, secure spike encoding, and hardware-level protections, are systematically categorized and assessed in the context of resource-constrained, event-driven platforms. Finally, we highlight emerging research directions in secure neuromorphic learning, such as continual and federated SNN training under adversarial settings, establishing a foundation for advancing the research in secure neuromorphic systems.

Computational methods in drug discovery significantly reduce both time and experimental costs. Nonetheless, certain computational tasks in drug discovery can be daunting with classical computing techniques which can be potentially overcome using quantum computing. A crucial task within this domain involves the functional classification of proteins. However, a challenge lies in adequately representing lengthy protein sequences given the limited number of qubits available in existing noisy quantum computers. We show that protein sequences can be thought of as sentences in natural language processing and can be parsed using the existing Quantum Natural Language framework into parameterized quantum circuits of reasonable qubits, which can be trained to solve various protein-related machine-learning problems. We classify proteins based on their sub-cellular locations—a pivotal task in bioinformatics that is key to understanding biological processes and disease mechanisms. Leveraging the quantum-enhanced processing capabilities, we demonstrate that Quantum Tensor Networks (QTN) can effectively handle the complexity and diversity of protein sequences. We present a detailed methodology that adapts QTN architectures to the nuanced requirements of protein data, supported by comprehensive experimental results. We demonstrate two distinct QTNs, inspired by classical recurrent neural networks (RNN) and convolutional neural networks (CNN), to solve the binary classification task mentioned above. Our top-performing quantum model has achieved a 94% accuracy rate, which is comparable to the performance of a classical model that uses the ESM2 protein language model embeddings. It’s noteworthy that the ESM2 model is extremely large, containing 8 million parameters in its smallest configuration, whereas our best quantum model requires only around 800 parameters. We demonstrate that these hybrid models exhibit promising performance, showcasing their potential to compete with classical models of similar complexity.

Modern integrated circuit (IC) design incorporates the usage of proprietary computer-aided design (CAD) software and integration of third-party hardware intellectual property (IP) cores. Subsequently, the fabrication process for the design takes place in untrustworthy offshore foundries that raises concerns regarding security and reliability. Hardware Trojans (HTs) are difficult to detect malicious modifications to IC that constitute a major threat, which if undetected prior to deployment, can lead to catastrophic functional failures or the unauthorized leakage of confidential information. Apart from the risks posed by rogue human agents, recent studies have shown that high-level synthesis (HLS) CAD software can serve as a potent attack vector for inserting HTs. In this article, we introduce a novel automated attack vector, which we term “HLS-IRT”, by inserting HT in the register transfer logic (RTL) description of circuits generated during an HLS based IC design flow, by directly modifying the compiler-generated intermediate representation (IR) corresponding to the design. We demonstrate the attack using a design and implementation flow based on the open-source Bambu HLS software and Xilinx FPGA, on several hardware accelerators spanning different application domains. Our results show that the resulting HTs are surreptitious and effective, while incurring minimal design overhead. We also propose a novel detection scheme for HLS-IRT, since existing techniques are found to be inadequate to detect the proposed HTs.

Hardware Trojans (HTs) are small circuits intentionally designed by an adversary for harmful purposes. These types of circuits are extremely difficult to detect. An HT often requires some specific signals to activate, which are almost impossible to discover. For this reason, test generation for side-channel analysis has gained significant attention in recent times and does not require HT activation. Such test generation techniques aim to generate a large amount of switching activity inside the HT circuit, increasing transient current measurement. However, such methods suffer from either long runtime or reliable results. In this work, a test generation technique is proposed based on the relative switching activity of the circuit to overcome the limitations of the existing works. Initially, the proposed technique measures the impact of each input on rare nets individually using random vector simulation. Potent inputs are selected to obtain a new set of test vectors that provide high relative switching inside a circuit. The proposed method is applied on 11 different ISCAS and 3 ITC 99 benchmark circuits. Experimental results endorse the efficacy of the proposed method outperforming traditional Hamming distance-based re-ordering techniques (up to 20×) while requiring a small runtime.