Demo Data from VLDB 2026 / reviewers in the wild / expert
Jacob N. Rohan
dblp:262/1195
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
High-performance computing · 56% Memory systems · 36% Hardware accelerators and domain-specific architectures · 8% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › in-memory computing
in-situ computing accelerator |
0.5 | 1 | 2021 | An Analog Preconditioner for Solving Linear Systems · HPCA 2021 |
High-performance computing › numerical linear algebra
preconditioner |
0.5 | 1 | 2021 | An Analog Preconditioner for Solving Linear Systems · HPCA 2021 |
High-performance computing
scientific computing |
0.5 | 1 | 2021 | An Analog Preconditioner for Solving Linear Systems · HPCA 2021 |
Memory systems › in-memory computing
in-situ analog computing |
0.1 | 1 | 2021 | An Analog Preconditioner for Solving Linear Systems · HPCA 2021 |
Hardware accelerators and domain-specific architectures
matrix-vector multiplication |
0.1 | 1 | 2021 | An Analog Preconditioner for Solving Linear Systems · HPCA 2021 |
Methods — techniques the papers use, named apart from their topics
domain decomposition · 0.5bit-slicing · 0.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2021 | An Analog Preconditioner for Solving Linear SystemsabstractOver the past decade as Moore's Law has slowed, the need for new forms of computation that can provide sustainable performance improvements has risen. A new method, called in situ computing, has shown great potential to accelerate matrix vector multiplication (MVM), an important kernel for a diverse range of applications from neural networks to scientific computing. Existing in situ accelerators for scientific computing, however, have a significant limitation: these accelerators provide no acceleration for preconditioning-a key bottleneck in linear solvers and in scientific computing workflows. This paper enables in situ acceleration for state-of-the-art linear solvers by demonstrating how to use a new in situ matrix inversion accelerator for analog preconditioning. As existing techniques that enable high precision and scalability for in situ MVM are inapplicable to in situ matrix inversion, new techniques to compensate for circuit non-idealities are proposed. Additionally, a new approach to bit slicing that enables splitting operands across multiple devices without external digital logic is proposed. For scalability, this paper demonstrates how in situ matrix inversion kernels can work in tandem with existing domain decomposition techniques to accelerate the solutions of arbitrarily large linear systems. The analog kernel can be directly integrated into existing preconditioning workflows, leveraging several well-optimized numerical linear algebra tools to improve the behavior of the circuit. The result is an analog preconditioner that is more effective (up to 50% fewer iterations) than the widely used incomplete LU factorization preconditioner, ILU(0), while also reducing the energy and execution time of each approximate solve operation by 1025x and 105x respectively. Ben Feinberg, Ryan Wong 0001, T. Patrick Xiao, Christopher H. Bennett, Jacob N. Rohan, Erik G. Boman, Matthew J. Marinella, Sapan Agarwal, Engin Ipek |
HPCA | 5 |