Placement is a critical step in the physical design, as it largely determines the potential for subsequent optimization. In this work, we propose a timing-driven detailed placement framework: first, a simplified RC-tree model is employed for flip-flop–buffer compensation; then, a gradient-augmented global heuristic algorithm is incorporated; and finally, timing improvement is achieved through local collaborative optimization. A comprehensive evaluation on eight ICCAD 2015 benchmarks demonstrates the effectiveness of our approach. Compared to DREAMPlace4.0-DP, a state-of-the-art timing-driven placer, our framework achieves an average improvement of 19.60% in WNS and 55.74% in TNS, while introducing less disturbance to the global placement. Moreover, it delivers a 0.80% reduction in HPWL and reduces runtime by 20.24%.

Timing optimization is critical to the entire design flow of the very-large-scale integrated (VLSI) circuit, and Global Placement is pivotal in achieving timing closure within the design flow of very-large-scale integration circuits. However, most global placement algorithms focus on optimizing wirelength rather than timing. Therefore, we propose a novel timing-driven global placement algorithm to address this gap. This paper proposes a timing-driven global placement algorithm utilizing a Nadam-based net-weighting strategy. Additionally, we employ a hybrid heuristic approach for adaptive dynamic adjustment of net weights. The experimental results on the ICCAD 2015 contest benchmarks show that compared to the RePlAce, our algorithm significantly improves WNS and TNS by 40.7% and 56.5%, respectively.

Timing-driven global placement is a critical phase in modern very-large-scale integration design, where minimizing total negative slack and worst negative slack is essential for achieving reliable timing closure. While prior works leverage pin-to-pin attraction and path-level timing analysis for optimization, their use of static weighting schemes limits adaptability to diverse critical path characteristics. In this paper, we present an enhanced timing-driven placement framework that introduces a novel entropy and node-aware pin-to-pin weighting strategy. For each pin pair, the weight is computed using its path entropy and the average number of logic nodes across associated critical paths, reflecting both slack concentration and path complexity. Furthermore, a dynamic balancing factor is incorporated to adaptively modulate the contribution of these two components during the optimization process. Experimental results on the ICCAD 2015 benchmark suite demonstrate that our approach significantly outperforms DREAMPlace 4.0, achieving an average improvement of$\mathbf{5 9. 3 9 \%}$in TNS and$\mathbf{2 7. 1 5 \%}$in WNS, along with noticeable reductions in half-perimeter wirelength.