Semiconductor supply chain vulnerability presents a significant obstacle to creating reliable systems. At various phases of the Integrated Circuit (IC) design life-cycle, malicious modifications, known as Hardware Trojans (HTs), can be introduced. Logic testing, a widely recognized approach for Automatic test pattern Generation (ATPG) in HT detection, encounters substantial challenges due to the vast complexity of the search space, making it impractical and leading to inadequate trigger coverage. This paper proposes a Particle Swarm Optimization (PSO) based method that leverages information on effective inputs to facilitate the detection of conditionally triggered ultra-small HTs. An evaluation of the technique on ISCAS-85 benchmarks reveals substantial improvements in trigger coverage and a notable reduction in runtime compared to state-of-the-art methods.

The global distribution of the semiconductor supply chain has heightened the risk of hardware Trojans (HTs), small malicious circuits that adversaries may embed during various stages of the system-on-chip (SoC) design process. Frequently implanted by untrusted third parties, these HTs can operate covertly and, when activated, pose a serious threat to the integrity, performance, and functionality of the system. Although there are promising test generation techniques for HT detection, they face two significant practical limitations: a lack of scalability for large designs and insufficient trigger coverage. The effective detection of HTs requires the application of appropriate test vectors. This paper introduces PATROL, a novel algorithm that combines Particle Swarm Optimization (PSO) and Genetic Algorithms (GA) within a scalable framework for the detection of HTs. This framework employs Automated Test Pattern Generation (ATPG)-based activation to achieve high trigger coverage. This approach significantly accelerates the convergence towards a solution while substantially improving the solution accuracy. Our experimental results demonstrate that our proposed method is more than 43 times faster and achieves an average increase in trigger coverage of more than 34%, significantly outperforming state-of-the-art test generation techniques for Trojan detection.

Assertion-based verification is a promising method that uses predefined rules, known as assertions, to check the functionality of hardware designs. The manual assertion definition is time-consuming and requires expert knowledge. Automatic assertion mining is gaining acceptance as a trustworthy method for assertion definition. Some automatic assertion miners extract assertions from simulation traces of the design, but the quality of mined assertions depends on the coverage of the stimuli used to generate the traces. Existing stimuli generation methods are either random or exhaustive. A random approach can only cover some design behavior, resulting in incomplete assertions. On the other hand, an exhaustive approach can cover all the design behavior but produces lengthy simulation traces that cause a high overhead for the miner. We propose a novel approach for stimul generation based on constraint random verification. A set of user-defined metrics then examines the generated stimuli to measure how much of the design specification has been exercised by the verification environment. Our approach uses a coverage model that defines, collects, and analyzes the design’s functionalities and identifies the gaps in the verification. The assertions generated by the proposed method have been compared with a well-known assertion miner, GoldMine. The result showed that our method detects $\mathbf{2 0 . 6 3 \%}$ more faults in the design than GoldMine in a shorter time. Moreover, it produces assertions that are about $\mathbf{7 9 \%}$ more effective.