Integrated Circuits (IC) are increasingly present in our daily lives through various everyday objects. Many third-party companies are involved during their manufacturing process. It introduces many threats to the ICs' manufacturing, such as IP piracy and Hardware Trojans. Strong Logic Locking methodology is generally used to protect from IC piracy, such as counterfeiting or reverse engineering, and against Hardware Trojans insertion; however, the lack of automated tools fully integrated into a CAD flow limits the integration of countermeasures. This paper proposes mathematical models on the Strong Logic Locking method to optimize the security and an automatic security design inserted in an open CAD flow. We implemented an exact algorithm to maximize the security measure while implementing a strategy to minimize the impact of delay and area on the circuit. This algorithm is a custom branch and bound based on the mathematical model developed in this paper. In addition, we propose a strategy to limit the impact of countermeasures on the delay. Furthermore, our approach takes place inside a standard open CAD flow after logic synthesis to be as generic as possible. The experiments carried out that security can be added in a standard open CAD flow with a reasonable computation time and a limited impact on the circuit. Our security measure is more precise than the previous one, with a limited area overhead defined by a user. The increase of the critical path is less than 7% for large benches with a limit of 10% area overhead.

In this work HLS is used for designing a parametric optical flow Hierarchical algorithm in FPGAs. The algorithm that is designed is the Hierarchical (pyramid) Horn and Schunck algorithm, both a multi-rate and multi-level (multi-scale) algorithm, which achieves larger motion displacement detection than the mono-scale ones. With the help of HLS, we parametrize our design in terms of the levels of the pyramid, the iteration factor and the number of pixels computed per clock. We are reusing the same resources in each level of the pyramid to keep the usage of DSPs and RAM low. We perform a design space exploration of the algorithm and we show that our fastest design achieves a throughput of 461 Mpixel/s in a 2048×2048 resolution pixel image.

This work proposes a highly tunable motion estimation architecture. We implement the Horn and Schunck algorithm with the hierarchical extension for larger motion estimations in FPGAs. Different architectures are explored dealing with interpolation, pipeline, parallelism and arithmetic format, in order to fit performance. We show in our exploration, how the different cores of our system should be used to increase the throughput. Our smallest design achieves a 30.8 Mpixel/s in a 1024×1024 resolution and the fastest 507 Mpixel/s which is one of the fastest ever achieved, as far as we know, for FPGAs.

The increasing need for validating heterogeneous Systems on Chip (SoC) before their costly fabrication gives rise to the development of numerous virtual prototyping tools, allowing not only the modeling of such systems, but also the simulation of the environment in which they will be embedded, including the crucial software. SoC designers indeed require flexible simulation frameworks that follow a component-based approach and that cover a wide field of physical/engineering disciplines... and no questions asked about the simulation intrinsics. Furthermore, for SMEs, laboratories, and enthusiastic makers with limited funding, the cost of these frameworks makes them unaffordable, especially when the target system hardware is supposed to be Open Source too. In this paper, we detail the principles of an Open Source SystemC Multi-Disciplinary Virtual Prototyping (SystemC MDVP) framework, which directly tackles with all these issues. We introduce the key concepts and methodology (relationships between Models of Computation and overall synchronization techniques) and insist on the importance of a “correct by construction” global model elaboration that allows to generate the hierarchy of solvers that make up the final simulator. We then show that a new Model of Computation, Electrical Network, has been added to SystemC MDVP to handle components with non-linear beahviors. The paper concludes with a quick presentation of the echOpen project which aims at designing a low-cost portable echography device modeled and simulated with the presented principles.

International audience