The interconnect (INT) micro-architecture of field programmable gate arrays (FPGAs) is critical for routability and performance of designs. Traditional method to evaluate robustness of INT involves comparing congestion of real or synthetic design implementations on competing INT architectures. This method conflates routing challenges with placement quality, floorplan constraints, and device utilization. To address this limitation, we propose a methodology, programmable congestion generator (PCG), that generates netlists with placement constraints to achieve targeted congestion stress, isolating directional or wirelength biases for architectural evaluation. Examples in this paper demonstrate the ability to induce congestion with precision, providing architects a direct means to validate hypotheses about routing resources. This work bridges the gap between existing benchmark-generation techniques and the practical requirements of INT design, offering a systematic framework to stress-test architectural innovations under quantifiable routing constraints.

Second language learners of British English (BE) are typically trained to learn four intonation classes - Glide-up, Glide-down, Dive and Take-off. We predict the intonation class in a learner's utterance by modeling the temporal dependencies in the pitch patterns with gated recurrent unit (GRU) networks. For these, we pre-train the GRU network using a set of synthesized pitch patterns representing each intonation class. For the synthesis, we propose to obtain pitch patterns from the tone sequences representing each intonation class obtained from domain knowledge. Experiments are conducted on speech data collected from experts in a spoken English training material for teaching BE intonation. The absolute improvements in the unweighted average recall (UAR) using the proposed scheme with pre-training are found to be 4.14 and 6.01 respectively over the proposed approach without pre-training and the baseline scheme that uses hidden Markov models (HMMs).