Recently, there has been a growing interest in leveraging Large Language Models for Verilog code generation. However, the current quality of the generated Verilog code remains suboptimal. This is largely due to the absence of well-defined, well-organized datasets with high-quality samples, as well as a lack of innovative fine-tuning methods and models specifically trained on Verilog. In this paper, we introduce a novel open-source dataset and a corresponding fine-tuning technique, which utilizes a multi-layered structure that we refer to as PyraNet. Our experiments demonstrate that employing the proposed dataset and fine-tuning approach leads to a more accurate fine-tuned model, producing syntactically and functionally correct Verilog code. The evaluation results show improvements by up-to 32.6% in comparison to the CodeLlama-7B baseline model and upto 16.7% in comparison to the state-of-the-art models using VerilogEval evaluation platform.

Modeling system-level behaviors of intricate System-on-Chip (SoC) designs is crucial for design analysis, testing, and validation. This paper presents an approach, AutoModel, to automatically inferring concise and abstract models from SoC communication traces, capturing the system-level protocols that govern co-ordinations among design blocks for various system functions. In this approach, a causality graph with annotations obtained from the SoC traces is constructed first. The annotated causality graph represents all potential causality relations among messages under consideration. Next, a constraint satisfaction problem is formulated from the causality graph, which is then solved by a satisfiability modulo theories (SMT) solver to find satisfying solutions. Finally, finite state models are extracted from the generated solutions, which can be used to explain and understand the input traces. The proposed approach is validated through experiments using synthetic traces obtained from simulating a transaction-level model of a multicore SoC design and traces collected from running real programs on a realistic multicore SoC modeled in gem5.