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VLDB 2026 Research / reviewers in the wild / expert

Deokho Seo

dblp:263/7482 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › non-volatile memory › persistent memory
byte-addressable persistent memory		 0.412020
NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces · HPCA 2020
Memory systems
memory interface		 0.412020
NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces · HPCA 2020
Memory systems
non-volatile memory		 0.412020
NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces · HPCA 2020
Memory systems › non-volatile memory › non-volatile main memory
NVDIMM		 0.412020
NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces · HPCA 2020

Methods — techniques the papers use, named apart from their topics

system-wide mechanisms · 0.4asynchronous timing support · 0.4
YearPublicationVenuePosition
2020 NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces
abstract
Currently, there are two representative non-volatile dual in-line memory module (NVDIMM) interfaces: a proprietary Intel DDR-T and the JEDEC NVDIMM-P, which are not supported by existing platforms. Adoption of new platform is costly and measuring its efficiency of migrating to the new platform is much more complex. This study is an alternative way of them—finding a new memory device that can be supported by all existing systems. In this paper, we propose an NVDIMM architecture with several system-wide mechanisms to allow the synchronous DDR4 memory interfaces to support non-deterministic (asynchronous) timing. The proposed memory architecture is implemented as a real device prototype, and also evaluated using synthetic and real workloads on an x86-64 server system.
Changmin Lee 0004, Wonjae Shin, Dae Jeong Kim, Yongjun Yu, Sung-Joon Kim, Taekyeong Ko, Deokho Seo, Kwanghee Lee, Seongho Choi 0002, Namhyung Kim, Vishak G, Arun George, Vishwas V, Donghun Lee 0001, Kang-Woo Choi, Changbin Song, Dohan Kim 0003, Insu Choi, Ilgyu Jung, Yong Ho Song, Jinman Han
 HPCA7