VLDB 2026 Research / reviewers in the wild / expert
Chanhee Jeon
dblp:264/0495
· DBLP profile ↗
3ranked-venue papers
2as first author
3since 2021 · last 2026
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author · 3 since 2021Software engineering, systems software and programming languages · 3 · 2 first-author · 3 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Reshaping Bayesian Optimization for Design Space Optimization Towards Accurate and Irredundant Evaluation in EDA Tool Parameter ExplorationabstractFinding an optimal tool parameter configuration that achieves optimal design PPA (performance, power, area) through Design Space Optimization (DSO) in Physical Design (PD) has become increasingly important due to the rising complexity of Electronic Design Automation (EDA) tool chains in modern VLSI design. DSO is particularly challenging due to the high dimensionality of tool parameters, the abundance of discrete parameter options, and, most critically, the non-linear relationship between parameters and design PPA. This work overcomes two limitations of the prior state-of-the-art Bayesian Optimization (BO) based DSO methods for EDA tool parameter optimization. The two limitations are (1) a poor correlation of the similarity computation in BO engine between two sampling points with the actual similarity between the corresponding post-layout PPAs, resulting in far from the Pareto-optimal PPA exploration; (2) redundant evaluations occur frequently when discrete parameters are quantized. Precisely, we overcome limitation 1 by training AE (AutoEncoder) model using PPA outcomes of the prior sample points and using it to reshape the latent parameter space such that similarity in latent vectors aligns with the similarity in PPA, thereby justifying the accurate kernel-based similarity function in BO, while we address limitation 2 by reformulating the acquisition function in BO in a way to effectively sample the discrete parameter values in the continuous design space. In the meantime, through experiments, it is shown that using our DSO method with reshaped BO amenable to EDA tool parameter optimization is able to find tool parameter options of 59% larger HyperVolume and up to 16% improvement for single objective (i.e., a weighted sum of PPA) optimization. Chanhee Jeon, Taewhan Kim 0001 |
DATE | 1 |
| 2026 | Consolidating ML-driven Early IR-drop Mitigation for Fast and Reliable IR-drop Closure
Munwon Lee, Chanhee Jeon |
DATE | 2 |
| 2024 | BOXGB: Design Parameter Optimization with Systematic Integration of Bayesian Optimization and XGBoostabstractFinding design flow parameters that ensure a high quality of final chip is a very important task, but requires an excessive amount of effort and time. In this work, we automate this task by proposing a machine learning (ML)-based design space optimization (DSO) framework. Rather than simply applying one ML model exclusively or multiple ones in a naive manner, we develop a comprehensive chain of ML engines which is able to explore the design parameter space more economically but effectively to make a fast convergence on finding the best parameter set. Specifically, we solve the DSO problem in three steps: (1) random sampling of parameter sets and then performing design evaluation to produce an initial ML training dataset; (2) iteratively, downsizing parameter dimension through Principal Component Analysis (PCA) followed by sampling through an exploration-centric mechanism which is internally driven by Bayesian Optimization (BO) and then evaluating the sample; (3) iteratively, sampling through an exploitation-centric mechanism driven by XGBoost regression and then checking anomaly by using XGBoost classification followed by evaluating the sample if it's not anomaly. From our experiments with benchmark designs, it is shown that our approach is able to find design parameter sets which are far better than that found by the prior state-of-the-art ML-based approaches, even with fewer number of design evaluations (i.e., EDA tool runs). In addition, in comparison with the designs produced by using the default parameter setting, our DSO framework is able to improve the design PPA metrics by$5\sim 30{\%}$I. Chanhee Jeon, Doyeon Won, Jaewan Yang, Kyu-Myung Choi, Taewhan Kim 0001 |
DATE | 1 |