Artificial Intelligence hardware accelerators are pervading the chip market. Most of the time, they are third-party IPs integrated by silicon manufacturers. As a consequence, their design may be obfuscated, which can introduce issues from a manufacturing testing perspective. This paper illustrates how to effectively and efficiently select the most appropriate functional stress stimuli for Artificial Intelligence (AI) Hardware (HW) Accelerators embedded in System-on-Chip (SoC). The proposed methodology is netlist independent; and it is based on both current measurements from the real chip and architectural evaluations. These ingredients are heuristically used to rank and sift the optimal functional patterns to apply along the Burn-In (BI) phase. Experimental results on two different Automotive SoCs manufactured by STMicroelectronics, demonstrate the effectiveness and efficiency of the proposed method.

Developing functional test programs for hardware testing is time-consuming and experience-wise. A functional test program’s quality is usually assessed only through expensive fault simulation campaigns during early development. This paper presents indirect quality measurements of fault detection capabilities of functional test programs to reduce the total cost of fault simulation in the early development stages. We present a methodology that analyzes the instruction trace generated by running functional test programs on-chip and building its control and dataflow graph. We use the graph to identify potential flaws that affect the program’s fault detection capabilities. We present different graph-based techniques to measure the programs’ quality indirectly. By exploiting standard debugging formats, we individuate instructions in the source code that affect the graph-based measurements. We perform experiments on an automotive device manufactured by STMicroelectronics, running functional test programs of different natures. Our results show that our metric allows test engineers to develop better functional test programs without basing their development solely on fault simulation campaigns.

This paper deals with functional System-Level Test (SLT) for System-on-Chips (SoCs) communication peripherals. The proposed methodology is based on analyzing the potential weaknesses of applied structural tests such as Scan-based. Then, the paper illustrates how to develop a functional SLT programs software suite to address such issues. In case the communication peripheral provides detection/correction features, the methodology proposes the design of a hardware companion module to be added to the Automatic Test Equipment (ATE) to interact with the SoC communication module by purposely corrupting data frames. Experimental results are obtained on an industrial, automotive SoC produced by STMicroelectronics focusing on the Controller Area Network (CAN) communication peripheral and showing the effectiveness of the SLT suite to complement structural tests.

Traditional structural tests are powerful automatic approaches for capturing faulty behavior in integrated circuits. Besides the ease of generating test patterns, structural methods are known to be able to cover a vast but incomplete spectrum of all possible faults in a System-on-Chip (SoC). A new step in the manufacturing test flow has been added to fill the leftover gaps of structural tests, called the System-Level Test (SLT), which resembles the final workload, and environment.This work illustrates how to build up an automated generation engine to synthesize SLT programs that effectively attack structural test weaknesses from both a holistic and an analytical perspective. The methodology targets the crossbar module, as one of the most critical areas in the SoC, and it simultaneously creates a ripple effect across the un-core logic.Experimental results are conducted on an automotive SoC manufactured by STMicroelectronics.

This paper explores the trade-offs of reducing scan test patterns during Wafer Sort, accepting additional packaging costs, and screening more chips during Package Tests. Previous works proposed ways of selecting or reordering patterns to bring the most efficient to the left. Unlike such studies, this work quantifies the benefit of removing patterns directly from the tail of any pattern set. The paper elaborates on novel formulas to propose a comprehensive cost model that combines yield, Wafer Sort, packaging, and Package Test costs. The model evolves from known concepts by assuming that mass production defectivity is non-uniformly distributed over the die population and accounts for sacrificial lots to extract guiding information. It is shown that reducing patterns at Wafer Sort is beneficial under certain conditions of yield, fault coverage, and considering equipment and production costs. The model accurately estimates the number of patterns to remove for maximum gain in these cases. As a further by-product, the paper shows that a significant cost advantage can be achieved if pattern generation is guided based on the basics of the non-uniform failure distribution. This approach is validated with an academic benchmark and by observing six months of production for a real-world microcontroller by STMicroelectronics.

Embedded nano-electronic devices have spread in daily life over the past ten years. Chip and embedded system manufacturing has thus become more challenging in recent years.When safety-critical sectors like the automobile are considered, addressing system anomalies and faults is crucial. Therefore, it is necessary to develop and research innovative ways to maintain high reliability in safety-critical sectors despite the complexity of present Systems-on-Chip (SoCs).In order to ensure high reliability, and be compliant with reliability standards, designers started to add additional circuitry to perform on-device tests. Built-In-Self-Test (BIST) is a technology that allows to conduct exhaustive tests within devices and, most importantly, without the need for external equipment. BIST can detect faults by outputting a signature at test end, which can be compared with a known value. Thus such known signatures are key, and in case of a signature mismatch it is not trivial to understand the root cause of the failure.This paper proposes a methodology to find the first failing pattern which causes the BIST’s signature to deviate and a way to collect good signatures from in-field devices, at key on/off, where BISTs are programmed and executed by the firmware at maximum frequency for an industrial case study produced by STMicroelectronics.The transition delay fault model is the primary target for the described work.

Functional test programs are increasingly used as flexible approaches to verify device functionality, both online (e.g., Software-Based Self Tests encapsulated in Software Test Library) and during the manufacturing test flow (e.g., System-Level Test). However, a traditional integrated development environment seldom analyzes functional test program weaknesses regarding fault-masking and propagation in CPU registers. Therefore, understanding the presence of errors in the programs due to logic faults at the end of the test program is only assessed by a signature computation, e.g., xor operation between all registers. The presence of program weaknesses in terms of data or control flow is not assessed, and it may lead to fault escapes and/or masking. In particular, those are perfect conditions for proliferating Silent data corruption and unrecoverable errors at the system level.This work aims to introduce a guided debugger-based fault injector framework to verify the fault propagation and masking capabilities of functional test programs by eventually catching program errors without relying on time-consuming simulation-based approaches. The fault-free instruction trace is dumped and analyzed to provide information about possible target registers of specific instructions for injecting faults, e.g., in jump instructions, where errors into registers may change the execution flow or not, to verify the presence of silent data corruptions and errors.The experimental results are carried out on an automotive device from the SPC58 family manufactured by STMicroelectronics, and faults are injected through a script running on Power Debug E40 from Lauterbach.

Burn-In test equipment usually owns extensive memory capabilities to store pre-computed patterns to be applied to the circuit inputs as well as ad-hoc circuitries to drive and read the DUT pins during the BI phase. The solution proposed in this paper dramatically reduces the memory size requirement and just demands a generic microcontroller unit (MCU) equipped with a couple of embedded processors, some standard common peripheral units, and a few KB memories. Moreover, the proposed Burn-In tester could be integrated into a System Level Test equipment which is typically based on MCUs to communicate functionally with the DUT. This paper provides full details about the architecture of such a low-cost innovative tester, which can supply the DUT with unlimited pseudo-random patterns created autonomously by the MCU firmware from any selected seed. The tester prototype developed to collect experimental results includes a low-cost System-on-Chip based on a multi-core MCU and a set of peripheral cores, encompassing timers and Direct Memory Access modules. The tester prototype is used to stress an automotive chip accounting for about 20 million gates, 700 thousand scan flip-flops, and several scan modes. The combination of pseudo-random pattern generation with the ability to control different scan and Design for Testability (DfT) modes, including LBIST, permits to reach a higher coverage of stress metrics than by the application of a limited set of pre-computed ATPG patterns. The toggle coverage level reached is up to 95.89%. The application speed achieved by the tester with non-optimized connections is up to about 10MHz.

The introduction of System Level Test (SLT) about a decade ago aimed to a better sustainability for the achievement of the quality objectives required by high performances GPUs and CPUs. The paper intends giving some quantitative information to support this simplified statement. To do this we will report the results of a study conducted by the industrial application of SLT on a product targeted to a high-quality market segment, such as automotive. The discussion will describe the different SLT solutions developed for this new field of application and how it was possible to isolate SLT-only fails and relative functional root causes and cross-correlate traditional ATE test versus SLT screening capability through manufacturing operations.