VLDB 2026 Research / reviewers in the wild / expert
Mohammadreza Rezvani
dblp:268/1910
· DBLP profile ↗
4ranked-venue papers
2as first author
3since 2021 · last 2026
0009-0009-2822-777XORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 2 · 1 first-author · 2 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Agile QoS-aware Dynamic Power Management with eBPF GovernorsabstractModern data center workloads present significant challenges to the existing dynamic power management (DPM) framework in Linux. Existing DPM frameworks trade off Quality of Service (QoS) awareness for responsiveness, oftentimes leaving significant energy-saving opportunities on the table. In this work, we present eBPF Governors, a framework to deliver highly responsive, low-overhead, QoS-aware dynamic power management by leveraging the benefits of eBPF, an emerging Linux kernel technology. Mohammadreza Rezvani, Daniel Wong 0001 |
ICS | 1 |
| 2026 | eBeeMetrics: An eBPF-based Library Framework for Feedback-free Observability of QoS MetricsabstractMany system management runtimes (SMRs), such as resource management and power management techniques, rely on quality-of-service (QoS) metrics, such as tail latency or throughput, as feedback. These QoS metrics are generally neither observable with hardware performance counters nor directly observable within the OS kernel. This introduces complexity and overhead in instrumenting the application and integrating QoS performance metric feedback with many management runtimes. To bridge this gap, we introduced eBeeMetrics, an eBPF-based library framework to accurately observe application-level metrics derived from only eBPF-observable events, such as system calls. eBeeMetrics can be used as a drop-in replacement to decouple system management runtimes from QoS metric feedback reporting, or can supplement existing QoS metrics to better identify server-side dynamics. eBeeMetrics achieves a strong correlation with real-world measured throughput and latency metrics across various latency-sensitive workloads. The eBeeMetrics tool is open-source; the source code is available at: https://github.com/Ibnathism/eBeeMetrics. Muntaka Ibnath, Mohammadreza Rezvani, Daniel Wong 0001 |
ISPASS | 2 |
| 2024 | Characterizing In-Kernel Observability of Latency-Sensitive Request-Level Metrics with eBPFabstractThis paper explores a novel server observability approach using eBPF (extended Berkeley Packet Filter) for detailed request-level performance metrics of data center latency-sensitive applications. Utilizing eBPF system call tracing, we evaluate if syscall activity can reconstruct high-level application behaviors and bypass the need for direct userspace reporting of performance metrics. Through careful selection of eBPF events, we demonstrate that certain syscall statistics can provide robust insight into request-level metrics. In addition, we demonstrate that these metrics can also be robust to networking effects, such as packet loss. By demonstrating the ability for eBPF to provide request-level observability, we can potentially enable many non-intrusive, low-overhead use cases for feedback in system management runtime frameworks, such as resource allocation, scheduling, and power management. Mohammadreza Rezvani, Ali Jahanshahi, Daniel Wong 0001 |
ISPASS | 1 |
| 2020 | High-Performance Parallel Radix Sort on FPGAabstractSorting is a key part in database operators (like duplicate elimination, sort-merge joins and group-by aggregations). Sorting billions of records in a fast and energy efficient manner has become a key research challenge. In this work, we explore sorting in-memory using a parallel version of Radix Sort to build a high-performance hardware accelerator, called HARS (Hardware Accelerated Radix Sort). Our design enables dividing the unsorted dataset among parallel engines without the need for a merge step. HARS is implemented on Micron’s SB-852 FPGA board. The proposed accelerator provides high throughput in-memory sorting at a rate of 44 Million 128-bit records per second. HARS is 1.4x faster than CPU and 1.36x faster than GPU when GPU bandwidth is normalized. Projected performance of a proposed board with a more capable FPGA chip would yield 1.25x higher throughput. Bashar Romanous, Mohammadreza Rezvani, Daniel Wong 0001, Evangelos E. Papalexakis, Vassilis J. Tsotras, Walid A. Najjar |
FCCM | 2 |