VLDB 2026 Research / reviewers in the wild / expert
Yubiao Pan
dblp:27/10459
· DBLP profile ↗
22ranked-venue papers
7as first author
12since 2021 · last 2026
0000-0003-1458-5911ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 21 · 7 first-author · 11 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021Security and privacy · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | SoKV: Scan performance optimization for KV separation with adaptive dynamic grouping and GC-based LSM-tree management
Yixiang Cai, Yubiao Pan, Xinwei Lin, Huizhen Zhang, Mingwei Lin |
Future Gener. Comput. Syst. | 2 |
| 2026 | VGKV: Variable granularity garbage collection with SSTable management for KV separation
Yixiang Cai, Yubiao Pan, Huizhen Zhang |
Future Gener. Comput. Syst. | 2 |
| 2026 | PROAD: Boosting Caffe Training via improving LevelDB I/O performance with Parallel Read, Out-of-Order Optimization, and Adaptive Design
Yubiao Pan, Ailing Tian, Huizhen Zhang |
Parallel Comput. | 1 |
| 2025 | Mitigating Resource Usage Dependency in Sorting-based KV Stores on Hybrid Storage Devices via Operation Decoupling
Yongkun Li 0001, Yubiao Pan, Haoting Tang, Yinlong Xu 0001 |
USENIX ATC | 3 |
| 2025 | CDNRocks: computable data nodes with RocksDB to improve the read performance of LSM-tree-based distributed key-value storage systems
Feixiong Huang, Yubiao Pan, Huizhen Zhang, Mingwei Lin |
J. Supercomput. | 2 |
| 2025 | RIOKV: reducing iterator overhead for efficient short-range query in LSM-tree-based key-value stores
Xinwei Lin, Yubiao Pan, Wenjuan Feng, Huizhen Zhang, Mingwei Lin |
J. Supercomput. | 2 |
| 2025 | PMCKV: pipeline-based multi-compactions KV stores to improve the system performance
Yubiao Pan, Yixiang Cai, Huizhen Zhang, Mingwei Lin |
J. Supercomput. | 1 |
| 2024 | CCFTL: A novel continuity compressed page-level flash address mapping method for SSDs
Liangkuan Su, Mingwei Lin, Yubiao Pan |
J. Parallel Distributed Comput. | 4 |
| 2024 | MTDB: an LSM-tree-based key-value store using a multi-tree structure to improve read performance
Xinwei Lin, Yubiao Pan, Wenjuan Feng, Huizhen Zhang, Mingwei Lin |
J. Supercomput. | 2 |
| 2023 | Traffic signal optimization control method based on adaptive weighted averaged double deep Q network
Youqing Chen, Huizhen Zhang, Minglei Liu, Yubiao Pan |
Appl. Intell. | 6 |
| 2022 | HCFTL: A Locality-Aware Flash Translation Layer for Efficient Address TranslationabstractIn modern solid-state drives (SSDs), a flash translation layer (FTL) is the core engine performing the logical-to-physical address translations. However, the increasing capacity of SSDs requires a large DRAM space to hold the mapping table in a page-level FTL. Due to the limited size of built-in DRAM, existing FTL schemes selectively cache some active mapping entries in DRAM, while store the entire mapping table on flash. However, the low cache hit ratio introduced by the traditional mapping entry eviction policy degrades the access performance of SSDs. In this article, we propose a novel FTL, hot-clusterity FTL (HCFTL), to improve the hit ratio of cached mapping table (CMT) of SSDs with limited cache space. HCFTL clusters mapping entries, which are newly evicted from the cache, into dynamic translation pages (DTPs). Reading entries from DTPs will increase the CMT hit ratio due to spatial and temporal localities. Because the logical page numbers (LPNs) in a DTP are not consecutive, we introduce two different efficient index structures to speedup the lookup of mapping entries in DTPs. Furthermore, to make the DTP index highly accurate, we additionally allocate an auxiliary cache to buffer the mapping entries newly evicted from CMT, and produce dynamic pages with minimum difference between the maximal and the minimal LPNs of entries in those pages. Our experiments show that HCFTL can improve the CMT hit ratio by up to 41.1% and decrease the system response time by up to 33.3%, compared to baseline FTL schemes. Yubiao Pan, Hao Chen 0080, Yinlong Xu 0001 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2021 | ECR: Eviction-cost-aware cache management policy for page-level flash-based SSDsabstractSummary Cache management policy plays a key role in offering low latency access to flash‐based SSDs. Most existing solutions including LRU and its successors only focus on improving the cache hit ratio, but rarely consider to reduce the waiting time of the eviction operation in the page‐level mapping FTLs. As the workloads spreading across internal chips of modern flash‐based SSDs are often highly imbalanced when workloads are write‐intensive, the time cost of evicting a dirty page from cache varies in a wide range. In this paper, we propose a novel eviction‐cost‐aware cache management policy, called ECR, to minimize the eviction cost in write‐dominant applications. ECR gives a higher probability to evict a page, which causes the shortest waiting time in the corresponding chip queue. To achieve this, we introduce a monitor module to keep track of states of all chip queues, and a multi‐LRU list structure to accelerate the selection of a victim chip and a target page in cache to perform an eviction. Our experimental results show that ECR can significantly reduce the average response time by as much as 59.55% and 44.84% compared to LRU and GCaR‐CFLRU, respectively, where GCaR‐CFLRU is the combination of state‐of‐the‐art algorithm GCaR and CFLRU. Hao Chen 0080, Yubiao Pan, Cheng Li 0001, Yinlong Xu 0001 |
Concurr. Comput. Pract. Exp. | 2 |
| 2019 | HCFTL: A Locality-Aware Page-Level Flash Translation LayerabstractThe increasing capacity of SSDs requires a large amount of built-in DRAM to hold the mapping information of logical-to-physical address translation. Due to the limited size of DRAM, existing FTL schemes selectively keep some active mapping entries in a Cached Mapping Table (CMT) in DRAM, while storing the entire mapping table on flash. To improve the CMT hit ratio with limited cache space on SSDs, in this paper, we propose a novel FTL, a hot-clusterity FTL (HCFTL) that clusters mapping entries recently evicted from the cache into dynamic translation pages (DTPs). Given the temporal localities that those hot entries are likely to be visited in near future, loading DTPs will increase the CMT hit ratio and thus improve the FTL performance. Furthermore, we introduce an index structure to speedup the lookup of mapping entries in DTPs. Our experiments show that HCFTL can improve the CMT hit ratio by up to 41.1% and decrease the system response time by up to 33.3%, compared to state-of-the-art FTL schemes. Hao Chen 0080, Cheng Li 0001, Yubiao Pan, Min Lyu, Yongkun Li 0001, Yinlong Xu 0001 |
DATE | 3 |
| 2019 | Lifetime-aware FTL to improve the lifetime and performance of solid-state drives
Yubiao Pan, Yongkun Li 0001, Huizhen Zhang, Yinlong Xu 0001 |
Future Gener. Comput. Syst. | 1 |
| 2018 | LCR: Load-Aware Cache Replacement Algorithm for Flash-Based SSDsabstractFlash-based SSDs are usually equipped with an onboard cache to further improve system performance by smoothing the gap between the upper-level applications and lower-level flash chips. Since modern SSDs are usually composed of multiple flash chips, and the load of flash chips are significantly different, it is very meaningful to be aware of the chip load condition when designing a cache replacement algorithm. Nevertheless, existing cache replacement algorithms only consider to reduce the cache miss ratio so as to reduce the I/O requests to the underlying flash memory as much as possible, none of them considers the load condition of flash chips. In this paper, we propose a Load- aware Cache Replacement algorithm, called LCR, to improve the performance of flash-based SSDs. The basic idea is to give a higher priority to cache the blocks on overloaded flash chips. We evaluate the performance of our scheme by using a trace- driven simulator with multiple real-world workloads, and results show that compared with the most common algorithm LRU and the state-of-the-art algorithm GCaR, LCR reduces the average response time by as much as 39.2% and 12.3%, respectively. Caiyin Liu, Min Lv, Yubiao Pan, Hao Chen 0080, Yongkun Li 0001, Cheng Li 0001, Yinlong Xu 0001 |
NAS | 3 |
| 2017 | ISM- An Intra-Stripe Data Migration Approach for RAID-5 ScalingabstractScaling is often carried out in modern RAID systems to meet the ever increasing demand of storage capacity and I/O performance. However, the scaling process of RAID-5 system is not trivial, due to its specific data/parity layout. Previous approaches of RAID-5 scaling require either migrating almost all data blocks in the system, or recalculating all or some of the parity blocks during scaling. This paper proposes a new RAID-5 scaling approach called ISM (Intra-Stripe Migration). With ISM, data migrations only happen within stripes, which means that the coding relationship among blocks remains the same. Therefore, the parity blocks do not need to be recalculated after data migration, which greatly reduces the I/O and computational costs. The properties of ISM approach can be summarized as follows: (1) it requires the minimum amount of data blocks to be migrated, (2) it supports data migration without recalculating parity blocks, and (3) it supports multiple successive scaling operations while keeping the above properties. The simulation results on DiskSim show that: (1) ISM reduces the scaling time from 47.91% to 87.01% and from 88.94% to 96.58% compared with GSR and ALV respectively in offline scaling, (2) under two real-world I/O traces, ISM also outperforms GSR by 64.15% to 87.30%, and ALV by 92.38% to 95.98% in scaling time, and (3) ISM maintains almost the same performance of data access with ALV and GSR after scaling. Yinlong Xu 0001, Yongkun Li 0001, Yubiao Pan |
NAS | 4 |
| 2017 | Workload-Aware Elastic Striping With Hot Data Identification for SSD RAID ArraysabstractRedundant array of independent disk (RAID) offers a good option to provide device-level fault tolerance for solid-state drives (SSDs). However, parity update with either read-modify-write or read-reconstruct-write may introduce a lot of extra I/Os and thus significantly degrades SSD RAID performance. To reduce the parity update cost, elastic striping chooses to reconstruct new stripes with only the newly updated data chunks instead of directly updating parity chunks. However, it necessitates an RAID-level garbage collection (GC) process, which may incur a very high cost due to the mixture of hot and cold data chunks. To address this problem, we follow the idea of elastic striping and propose a workload-aware scheme (WAS) to reduce the RAID-level GC cost so as to improve the performance and endurance of SSD RAID. In particular, we first develop a novel lightweight hot data identification scheme which requires only a very small computation time and memory cost, then propose a hotness-aware elastic striping approach to separately write data chunks with different hotness to different regions in SSD RAID. To evaluate the effectiveness and efficiency of our WAS, we implement a prototype system on RAID-5 and RAID-6 arrays composed of commercial SSDs. Experimental results show that compared to original elastic striping, our scheme reduces 30.0%-70.6% (and 23.9%-63.2%) of chunk writes under the RAID-5 (and RAID-6) settings, and also reduces the average response time by 60.9%-79.3% (and 56.8%-80.9%) for RAID-5 (and RAID-6), respectively. Besides, our scheme also improves the endurance and reliability of SSD RAID compared to original elastic striping. Yongkun Li 0001, Biaobiao Shen, Yubiao Pan, Yinlong Xu 0001, Zhipeng Li 0005, John C. S. Lui |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 2016 | DCS: Diagonal Coding Scheme for Enhancing the Endurance of SSD-Based RAID ArraysabstractTo guarantee high reliability, solid-state drive (SSD)-based storage systems require data redundancy schemes, e.g., redundant array of independent disks (RAID) schemes. Traditional RAID-5, RAID-6, and Reed-Solomon codes can tolerate one, two, and an arbitrary number of device failures, respectively. However, some SSDs under those redundant configurations may age much faster than others because of the high skewness and locality of workloads. The uneven aging rates may make some SSDs wear out very quickly and decrease the endurance of SSD-based RAID arrays. To address this problem, we first come up with a diagonal coding scheme (DCS) by distributing the updating dependencies evenly among devices to improve the system-level wear-leveling. DCS can efficiently improve the array endurance if requests are aligned with the stripe size, i.e., when data symbols in the same stripe receive the same number of writes, while the number could be different for different stripes. To relax the above assumption, we further propose an enhanced scheme, DCS+. With a buffer design, DCS+ can improve the wear-leveling among devices under general access patterns via triggering different responses to different kinds of requests. We conduct extensive trace-driven evaluations based on real-world workloads, and results show that our design efficiently enhances the endurance of SSD-based RAID arrays. Yubiao Pan, Yongkun Li 0001, Yinlong Xu 0001, Biaobiao Shen |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2015 | Grouping-Based Elastic Striping with Hotness Awareness for Improving SSD RAID PerformanceabstractRAID provides a good option to provide device-level fault tolerance. Conventional RAID usually updates parities with read-modify-write or read-reconstruct-write, which may introduce a lot of extra I/Os and thus significantly degrade SSD RAID performance. The recently proposed elastic striping scheme reconstructs new stripes with updated new data chunks without updating old parity chunks. However, it necessitates RAID-level garbage collection which may incur a very high cost. In this paper, we propose a hotness-aware caching scheme to buffer incoming writes and categorize data chunks in buffers into multiple groups according to their hotness values. We then propose a grouping-based elastic striping scheme to separately write data chunks in different groups into SSDs. We deployed the proposed schemes on a RAID-5 array composed of eight commercial SSDs, and experimental results show that compared to elastic striping, our scheme reduces 26% -- 65% of chunk writes to SSDs, and also reduces the average response time by 17.2% -- 63.9%. Yubiao Pan, Yongkun Li 0001, Yinlong Xu 0001, Zhipeng Li 0005 |
DSN | 1 |
| 2015 | A Light-Weight Hot Data Identification Scheme via Grouping-based LRU Lists
Biaobiao Shen, Yongkun Li 0001, Yinlong Xu 0001, Yubiao Pan |
ICA3PP (4) | 4 |
| 2014 | DCS5: Diagonal Coding Scheme for Enhancing the Endurance of SSD-Based RAID-5 SystemsabstractSolid-state drives (SSDs) have been widely deployed in large-scale storage systems. To guarantee high reliability for SSD-based storage systems, it still requires data redundancy schemes, e.g., RAID schemes. Traditional RAID-5 shows its benefits in load-balancing and I/O parallelism, and so it is still the first choice for enhancing the reliability of SSD RAID arrays. However, some SSDs under the RAID-5 configuration may age much faster than others because of the non-uniformity of workloads, which makes them be worn out very quickly and so decreases the endurance of SSD-based RAID arrays. To address this problem, we develop a diagonal coding scheme, DCS5, to improve the wear-leveling among devices in an SSD-based RAID-5 array. DCS5 can efficiently improve the array endurance if accesses are aligned with the stripe size, i.e., When data symbols in the same stripe receive the same number of writes, while the number could be different for different stripes. To relax the above assumption, we further propose an enhanced scheme which is called as DCS5+. DCS5+ can improve the wear-leveling among devices under general access patterns via triggering different responses to different kinds of requests. We conduct extensive trace-driven evaluations based on real-world workloads, and results show that our coding scheme efficiently enhances the endurance of SSD-based RAID-5 arrays. Yubiao Pan, Yongkun Li 0001, Yinlong Xu 0001 |
NAS | 1 |
| 2011 | A Hybrid Approach to Failed Disk Recovery Using RAID-6 Codes: Algorithms and Performance EvaluationabstractThe current parallel storage systems use thousands of inexpensive disks to meet the storage requirement of applications. Data redundancy and/or coding are used to enhance data availability, for instance, Row-diagonal parity (RDP) and EVENODD codes, which are widely used in RAID-6 storage systems, provide data availability with up to two disk failures . To reduce the probability of data unavailability, whenever a single disk fails, disk recovery will be carried out. We find that the conventional recovery schemes of RDP and EVENODD codes for a single failed disk only use one parity disk. However, there are two parity disks in the system, and both can be used for single disk failure recovery. In this article, we propose a hybrid recovery approach that uses both parities for single disk failure recovery, and we design efficient recovery schemes for RDP code (RDOR-RDP) and EVENODD code (RDOR-EVENODD). Our recovery scheme has the following attractive properties: (1) “ read optimality ” in the sense that our scheme issues the smallest number of disk reads to recover a single failed disk and it reduces approximately 1/4 of disk reads compared with conventional schemes; (2) “ load balancing property ” in that all surviving disks will be subjected to the same (or almost the same) amount of additional workload in rebuilding the failed disk. We carry out performance evaluation to quantify the merits of RDOR-RDP and RDOR-EVENODD on some widely used disks with DiskSim. The offline experimental results show that RDOR-RDP and RDOR-EVENODD outperform the conventional recovery schemes of RDP and EVENODD codes in terms of total recovery time and recovery workload on individual surviving disk. However, the improvements are less than the theoretical value (approximately 25%), as RDOR-RDP and RDOR-EVENODD change the disk access pattern from purely sequential to a more random one compared with their conventional schemes. Liping Xiang, Yinlong Xu 0001, John C. S. Lui, Qian Chang, Yubiao Pan, Runhui Li |
ACM Trans. Storage | 5 |