Multipath is a challenging problem for radar-based localization systems, especially in indoor scenarios. Multipath is caused by the bounces from static objects like walls and furniture in the room creating false alarms (“ghosts”) in target detections. Although solutions for the multipath effect have been proposed for a range of radar sensing problems, the specific case of multipath recognition and mitigation for a colocated multiple-input–multiple-output (MIMO) radar remains unsolved. For MIMO radar, the different direction-of-arrival (DoA) and direction-of-departure (DoD) angles inhibit the use of beamforming with a virtual array for localizing the first-order ghosts. Additionally, the prior knowledge of the multipath geometry model (room layout and boundary) is not always accessible. Classical ray tracing methods to resolve multipath are hence, not practical. In this work, we exploit a linear relationship between the target and multipath ghosts in the range-Doppler map to propose a Hough-transform-based multipath recognition solution. The algorithm does not require prior multipath geometry information and applies to the various indoor environments for an MIMO radar. Simulation and measurement results demonstrate the effectiveness of the proposed algorithm.

Autonomous driving is disrupting the automotive industry as we know it today. For this, fail-operational behavior is essential in the sense, plan, and act stages of the automation chain in order to handle safety-critical situations on its own, which currently is not reached with state-of-the-art approaches.The European ECSEL research project PRYSTINE realizes Fail-operational Urban Surround perceptION (FUSION) based on robust Radar and LiDAR sensor fusion and control functions in order to enable safe automated driving in urban and rural environments. This paper showcases some of the key exploitable results (e.g., novel Radar sensors, innovative embedded control and E/E architectures, pioneering sensor fusion approaches, AI-controlled vehicle demonstrators) achieved until its final year 3.

As processors continue to get exponentially cheaper for end users following Moore’s law, the costs involved in their design keep growing, also at an exponential rate. The reason is ever increasing complexity of processors, which modern EDA tools struggle to keep up with. This paper focuses on the design of Instruction Set Architecture (ISA), a significant part of the whole processor design flow. Optimal design of an instruction set for a particular combination of available hardware resources and software requirements is crucial for building processors with high performance and energy efficiency, and is a challenging task involving a lot of heuristics and high-level design decisions. This paper presents a new compositional approach to formal specification and synthesis of ISAs. The approach is based on a new formalism, called Conditional Partial Order Graphs, capable of capturing common behavioural patterns shared by processor instructions, and therefore providing a very compact and efficient way to represent and manipulate ISAs. The Event-B modelling framework is used as a formal specification and verification back-end to guarantee correctness of ISA specifications. We demonstrate benefits of the presented methodology on several examples, including Intel 8051 microcontroller.

In the last decade we have witnessed a steady trend towards functional diversification of hardware, because an application specific hardware component is a lot easier to design and optimise than a general-purpose one. Therefore, a modern microelectronics system often contains several application specific cores, each targeted for a particular function. As operating conditions issues are becoming more important, we start to see non-functional diversification in terms of performance and energy consumption; it is expected that a system can operate in a wide spectrum of environmental conditions and it should support a hierarchy of energy-saving modes. As a result, "mode-specific" processing cores are gaining popularity. The number of possible combinations of functional and nonfunctional variations of hardware components is becoming unmanageable and is leading to inefficient silicon utilisation. In this paper we explore a novel approach to hardware design which allows building computation systems capable of adjusting to operating conditions through dynamic reconfiguration. We demonstrate the approach by designing an asynchronous microprocessor core that can operate in a wide range of supply voltages and can adjust its functionality towards a specific application and operating mode. Our methodology is based on a novel model of hardware description and on self-timed design techniques.

Instruction sets of modern processors contain hundreds of instructions defined on a relatively small set of datapath components and distinguished by their codes and the order in which they activate these components. Optimal design of an instruction set for a particular combination of available hardware components and software requirements is crucial for system performance and is a challenging task involving a lot of heuristics and high-level design decisions. The overall design process is significantly complicated by inefficient representation of instructions, which are usually described individually despite the fact that they share a lot of common behavioural patterns. This paper presents a new methodology for compact graph representation of processor instruction sets, which gives the designer a new high-level perspective for reasoning on large sets of instructions without having to look at each of them individually. This opens the way for various transformation and optimisation procedures, which are formally defined and explained on several examples, as well as practically evaluated on an FPGA platform.