Demo Data from VLDB 2026 / reviewers in the wild / expert
Alina Deutsch
dblp:27/1240
· DBLP profile ↗
9ranked-venue papers
2as first author
0since 2021 · last 2011
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 7Applied, interdisciplinary, general and emerging computing · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Interconnection networks and networks-on-chip · 28% Electronic design automation · 26% Integrated circuit design · 20% |
Topics — the 8 heaviest of 10, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Interconnection networks and networks-on-chip
high-speed interconnect |
0.1 | 1 | 2008 | Low power passive equalizer optimization using tritonic step response · DAC 2008 |
High-performance computing › supercomputing
bluegene/l |
0.0 | 1 | 2002 | An overview of the BlueGene/L Supercomputer · SC 2002 |
High-performance computing
supercomputing |
0.0 | 1 | 2002 | An overview of the BlueGene/L Supercomputer · SC 2002 |
Integrated circuit design
system-on-chip |
0.0 | 1 | 2002 | An overview of the BlueGene/L Supercomputer · SC 2002 |
Electronic design automation
signal integrity |
0.0 | 2 | 2008 | Low power passive equalizer optimization using tritonic step response · DAC 2008 On-chip wiring design challenges for gigahertz operation · Proc. IEEE 2001 |
Electronic design automation › interconnect modeling
on-chip interconnect modeling |
0.0 | 1 | 2001 | On-chip wiring design challenges for gigahertz operation · Proc. IEEE 2001 |
Electronic design automation › interconnect modeling
transmission line modeling |
0.0 | 1 | 2001 | On-chip wiring design challenges for gigahertz operation · Proc. IEEE 2001 |
Interconnection networks and networks-on-chip
interconnect characterization |
0.0 | 1 | 1998 | Electrical characteristics of interconnections for high-performance systems · Proc. IEEE 1998 |
Methods — techniques the papers use, named apart from their topics
tritonic step response analysis · 0.1system architecture design · 0.0performance scaling studies · 0.0electromagnetic simulation · 0.0RC circuit modeling · 0.0transmission-line theory · 0.0crosstalk modeling · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2011 | Prediction and Comparison of High-Performance On-Chip Global InterconnectionabstractAs process technology scales, numerous interconnect schemes have been proposed to mitigate the performance degradation caused by the scaling of on-chip global wires. In this paper, we review current on-chip global interconnect structures and develop simple models to analyze their architecture-level performance. We propose a general framework to design and optimize a new category of global interconnect based on on-chip transmission line (T-line) technology. We perform a group of experiments using six different global interconnection structures to discover their differences in terms of latency, energy per bit, throughput, area, and signal integrity over several technology nodes. Our results show that T-line structures have the potential to outperform conventional repeated RC wires at future technology nodes to achieve higher performance while using less power and improving the reliability of wire communication. Our results also show that on-chip equalization is helpful to improve throughput, signal integrity, and power efficiency. Yulei Zhang 0002, Alina Deutsch, Arif Ege Engin, James F. Buckwalter, Chung-Kuan Cheng |
IEEE Trans. Very Large Scale Integr. Syst. | 3 |
| 2009 | Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologiesabstractAccurate and fast estimation of VLSI interconnect thermal profiles has become critically important to estimate their impact on circuit/system performance and reliability, which is necessary for reducing product development time and achieving first-pass silicon success. Present commercial thermal analysis tools are incapable of simulating complex structures, particularly in the 3-D domain and are also difficult to integrate with existing design tools. Existing analytical thermal models are not perfect either: they are either not accurate enough or oversimplified. This paper uses a methodology, which exploits existing electrical resistance solvers for thermal simulation, to allow fast acquisition of thermal profiles of complex interconnect structures with good accuracy and reasonable computation cost. Moreover, for the first time, an accurate closed-form thermal model is developed. The model allows for an equivalent medium with effective thermal conductivity (isotropic or anisotropic) to replace the detailed material information in non-critical regions so that complex interconnect structures can be simulated. Using these techniques, this paper demonstrates the simulation of a very complex interconnect structure (~9000 objects or 15 million meshed unknowns after first order isotropic equivalent medium replacement), which is a first time achievement in the area of interconnect thermal analysis. On the other hand, it is shown that an anisotropic equivalent medium is a much better approximation of real interconnect structures from the point of view of accuracy and computation. Lijun Jiang, Seshadri K. Kolluri, Barry J. Rubin, Alina Deutsch, Howard H. Smith, Kaustav Banerjee |
ICCAD | 5 |
| 2008 | Low power passive equalizer optimization using tritonic step responseabstractA low power passive equalizer using RL terminator is proposed and optimized in this work. The equalizer includes an inductor in series with the resistive terminator, which boosts high frequency components and therefore improves the interconnect bandwidth with little overhead on power consumption. An analytic estimation method for eye-opening and jitter based on tritonic step response is also introduced in this work, which enables the optimization procedure. Our experimental results show that our estimation method is accurate and a board level transmission line of 50cm wire length can achieve 15Gb/s data rate. With 15GHz frequency input, the power consumption of the equalizer is less than 2.5mW, and the total power is 5mW. Wenjian Yu, Haikun Zhu, Alina Deutsch, George A. Katopis, Daniel M. Dreps, Ernest S. Kuh, Chung-Kuan Cheng |
DAC | 4 |
| 2004 | A CAD Methodology and Tool for the Characterization of Wide On-Chip BusesabstractIn this paper, we describe a CAD methodology for the full electrical characterization of high-performance, on-chip data buses. The goal of this methodology is to allow the accurate modeling and analysis of wide, on-chip data buses as early as possible in the design cycle. The modeling is based on a manufacturing (rather than design-manual) description of the back-end-of-the-line (BEOL) cross section of a given technology and on a full yet contained description of the power-ground mesh in which the data bus is embedded. One major aspect of the resulting electrical models is that they allow the designer to evaluate the wide bus from the three viewpoints of signal timing, crosstalk (both inductive and capacitive), and common-mode signal integrity. Another major aspect is that they take into account such important high-frequency phenomena as the dependence of the current return-path resistance on frequencies. The CAD methodology described in this paper has been extensively correlated with on-chip hardware measurements. Ibrahim M. Elfadel, Alina Deutsch, Gerard V. Kopcsay, Bradley Rubin, Howard H. Smith |
DATE | 2 |
| 2002 | Blue Gene/L, a System-On-A-ChipabstractSummary form only given. Large powerful networks coupled to state-of-the-art processors have traditionally dominated supercomputing. As technology advances, this approach is likely to be challenged by a more cost-effective System-On-A-Chip approach, with higher levels of system integration. The scalability of applications to architectures with tens to hundreds of thousands of processors is critical to the success of this approach. Significant progress has been made in mapping numerous compute-intensive applications, many of them grand challenges, to parallel architectures. Applications hoping to efficiently execute on future supercomputers of any architecture must be coded in a manner consistent with an enormous degree of parallelism. The BG/L program is developing a peak nominal 180 TFLOPS (360 TFLOPS for some applications) supercomputer to serve a broad range of science applications. BG/L generalizes QCDOC, the first System-On-A-Chip supercomputer that is expected in 2003. BG/L consists of 65,536 nodes, and contains five integrated networks: a 3D torus, a combining tree, a Gb Ethernet network, barrier/global interrupt network and JTAG. George S. Almási, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen 0005, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, Alina Deutsch, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, Blake G. Fitch, Joseph Gagliano, Alan Gara, Robert S. Germain, Mark Giampapa, Manish Gupta 0002, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David F. Heidel, Philip Heidelberger, Lorraine M. Herger, Dirk Hoenicke, T. Jamal-Eddine, Gerard V. Kopcsay, Alphonso P. Lanzetta, Derek Lieber, M. Lu, Mark P. Mendell, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Rick A. Rand, Richard D. Regan, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, Sarabjeet Singh, Peilin Song, Burkhard D. Steinmacher-Burow, Karin Strauss, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, J. Brown, Thomas A. Liebsch, A. Schram, G. Ulsh |
CLUSTER | 18 |
| 2002 | An overview of the BlueGene/L SupercomputerabstractThis paper gives an overview of the BlueGene/L Supercomputer. This is a jointly funded research partnership between IBM and the Lawrence Livermore National Laboratory as part of the United States Department of Energy ASCI Advanced Architecture Research Program. Application performance and scaling studies have recently been initiated with partners at a number of academic and government institutions,including the San Diego Supercomputer Center and the California Institute of Technology. This massively parallel system of 65,536 nodes is based on a new architecture that exploits system-on-a-chip technology to deliver target peak processing power of 360 teraFLOPS (trillion floating-point operations per second). The machine is scheduled to be operational in the 2004-2005 time frame, at price/performance and power consumption/performance targets unobtainable with conventional architectures. Narasimha R. Adiga, Gheorghe Almási 0001, George S. Almási, Yariv Aridor, Rajkishore Barik, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Waiman Chan, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen 0005, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, K. M. Desai, Alina Deutsch, Tamar Domany, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, C. Christopher Erway, J. Esch, Blake G. Fitch, Joseph Gagliano, Alan Gara, Rahul Garg 0001, Robert S. Germain, Mark Giampapa, Balaji Gopalsamy, John A. Gunnels, Manish Gupta 0002, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David F. Heidel, Philip Heidelberger, Lorraine M. Herger, Dirk Hoenicke, R. D. Jackson, T. Jamal-Eddine, Gerard V. Kopcsay, Elie Krevat, Manish P. Kurhekar, Alphonso P. Lanzetta, Derek Lieber, L. K. Liu, M. Lu, Mark P. Mendell, A. Misra, Yosef Moatti, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Adam J. Oliner, Vinayaka Pandit, R. B. Pudota, Rick A. Rand, Richard D. Regan, Bradley Rubin, Albert E. Ruehli, Silvius Vasile Rus, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, M. Sharma, Edi Shmueli, Sarabjeet Singh, Peilin Song, Vijay Srinivasan, Burkhard D. Steinmacher-Burow, Karin Strauss, Christopher W. Surovic, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Arun R. Umamaheshwaran, P. Verma, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, W. Barrett, C. Engel, B. Drehmel, B. Hilgart, D. Hill, F. Kasemkhani, David J. Krolak, Chun-Tao Li 0001, Thomas A. Liebsch, James A. Marcella, A. Muff, A. Okomo, M. Rouse, A. Schram, M. Tubbs, G. Ulsh, Charles D. Wait, J. Wittrup, Myung Bae, Kenneth A. Dockser, Lynn Kissel, Mark K. Seager, Jeffrey S. Vetter, K. Yates |
SC | 24 |
| 2002 | A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesisabstractAlthough three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis. Gerard V. Kopcsay, Byron Krauter, David Widiger, Alina Deutsch, Barry J. Rubin, Howard H. Smith |
IEEE Trans. Very Large Scale Integr. Syst. | 4 |
| 2001 | On-chip wiring design challenges for gigahertz operationabstractThis paper reviews the status of present day on-chip wiring design methodologies and understanding. A brief explanation is given of the fundamental transmission-line properties that should be considered for accurate prediction of crosstalk, common-mode noise and clock skew. The deficiencies of RC-circuit representation are highlighted and design guidelines are given for using modeling and simulation techniques that have been previously used for package interconnections. Such techniques are believed to teach designers how to make better use of available technologies and help them architect systems that operate with many-GHz clock rates. Alina Deutsch, Paul Coteus, Gerard V. Kopcsay, Howard H. Smith, Christopher W. Surovic, Byron Krauter, Daniel C. Edelstein, Phillip J. Restle |
Proc. IEEE | 1 |
| 1998 | Electrical characteristics of interconnections for high-performance systemsabstractA review is presented of the electrical characteristics of high-density, high-performance interconnections used in digital and communication applications. These interconnections behave as lossy transmission lines for the frequency range of interest. A brief theoretical explanation of the key properties of lossy, coupled transmission lines is given. A new short-pulse propagation technique used for characterizing a large category of wiring is described. A detailed description is made of each of the major interconnect types encountered namely, shielded cables, printed circuit boards, ceramic carriers, thin-film wiring, and on-chip wiring. Representative examples are given in each case to highlight the key performance-limiting parameters. The modeling and measurement techniques used are explained and examples are given. Future technological directions and their effect on performance are discussed. Alina Deutsch |
Proc. IEEE | 1 |