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Khai D. T. Ngo

dblp:27/2410 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 2007
0000-0002-0326-3055ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
circuit simulation
0.012004
Efficient simulation of coupled circuit-field problems: generalized Falk method · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004
Electronic design automation › circuit simulation
model order reduction
0.012004
Efficient simulation of coupled circuit-field problems: generalized Falk method · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004
Electronic design automation
electromagnetic simulation
0.012004
Efficient simulation of coupled circuit-field problems: generalized Falk method · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004

Methods — techniques the papers use, named apart from their topics

lanczos-type methods · 0.0generalized falk method · 0.0finite element method · 0.0
YearPublicationVenuePosition
2007 Digital Inverse Timing Generator with Wide Dynamic Range
abstract
This paper addresses a timing generator with an output inversely proportional to a binary input without involving cost/area intensive digital division hardware or DSP processor based solution. The timing generation is based on interpreting a binary input as a floating point number (step value) and successively accumulating it to a predefined count. A unique scaling process generates the step value required for accumulation from the binary input and also alleviates the requirement for a high clock frequency. The functionality of the proposed architecture was experimentally verified with implementation on an ALTERA CPLD EPF10K70 clocked at 25.175MHz. The dynamic range extends from 355ns to 17μs.
Bharath Balaji Kannan, Khai D. T. Ngo
ISCAS2
2004 Efficient simulation of coupled circuit-field problems: generalized Falk method
abstract
The proposed generalized Falk (GF) method offers an extremely simple and convenient way to solve coupled circuit-field problems in circuit simulators by transforming the discretized governing-field equations into guaranteed stable-and-passive one-dimensional (1D) equivalent-circuit systems, which are then combined with the circuit part of the overall coupled problem. More efficient than the traditional Lanczos-type methods, the GF method transforms a general finite-element system represented by a system of full matrices into an identity capacitance (mass) matrix and a tridiagonal conductance (stiffness) matrix. No positive poles are produced; all transformed matrices remain positive definite. The resulting 1D equivalent-circuit system contains only resistors, capacitors, inductors, and current sources. Several numerical examples are provided.
Loc Vu-Quoc, Yuhu Zhai, Khai D. T. Ngo
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
2000 Graphical DC analysis of three-phase PWM converters using a complex transformation
abstract
A graphical complex transformation technique is described for the analysis of balanced three-phase converters in the rotation reference frame. The technique avoids the cumbersome matrix manipulation of the equation form of the complex transformation, and the coupling between the subcircuits resulting from the real (dq) transformation. It uses symmetric and decoupled equivalent circuits to graphically analyze three-phase converters, thus greatly simplifying the analysis procedure. All three-phase circuit components are modeled in the transformed coordinates, where all circuit parameters are constant under steady state. The application of the technique is demonstrated for the boost inverter.
Khai D. T. Ngo
ISCAS3