The increasing complexity and parameter count of Convolutional Neural Networks (CNNs) and Transformers pose challenges in terms of computational efficiency and resource demands. Pruning has been identified as an effective strategy to address these challenges by removing redundant elements such as neurons, channels, or connections, thereby enhancing computational efficiency without heavily compromising performance. This paper builds on the foundational work of Optimal Brain Damage (OBD) by advancing the methodology of parameter importance estimation using the Hessian matrix. Unlike previous approaches that rely on approximations, we introduce Optimal Brain Apoptosis (OBA), a novel pruning method that calculates the Hessian-vector product value directly for each parameter. By decomposing the Hessian matrix across network layers and identifying conditions under which inter-layer Hessian submatrices are non-zero, we propose a highly efficient technique for computing the second-order Taylor expansion of parameters. This approach allows for a more precise pruning process, particularly in the context of CNNs and Transformers, as validated in our experiments including VGG19, ResNet32, ResNet50, and ViT-B/16 on CIFAR10, CIFAR100 and Imagenet datasets. Our code is available at https://github.com/NEU-REAL/OBA.

Sparse and asynchronous sensing and processing in natural organisms lead to ultra low-latency and energy-efficient perception. Inspired by these characteristics, event cameras have attracted extensive attention from academia and industry. However, the mainstream event stream processing paradigms (e.g., event frames, 3D voxels) encounter issues such as feature loss, event stacking, and high computational burden. These problems deviate from the intended purpose of event cameras. To address these issues, we propose a fully asynchronous neuromorphic paradigm that integrates event cameras, spiking networks, and neuromorphic processors (Intel Loihi). This paradigm can faithfully process each event asynchronously as it arrives, mimicking the spike-driven signal processing in biological brains. We first propose a Key-Event-Point module to extract the key event stream from the raw event stream, effectively addressing the issue of limited transmission bandwidth when processing events on neuromorphic processors. Then, we propose the complete pipeline for the dodging network based on spiking neural networks to achieve offline training and online inference. Finally, we compare the proposed paradigm with event frames and 3D voxels processing paradigms in detail on the real mobile robot dodging task. Experimental results show that our scheme exhibits better robustness than image-like methods with different time windows and light conditions. Additionally, the energy consumption per inference of our scheme on the embedded Loihi processor is only 4.30% of that of the event spike tensor method on NVIDIA Jetson Orin NX with energy-saving mode, and 1.64% of that of the event frame method on the same neuromorphic processor. To the best of our knowledge, this is the first time that a fully asynchronous neuromorphic paradigm has been implemented for solving sequential tasks on a real mobile robot.Note to Practitioners—As a neuromorphic visual sensor, the event camera offers a novel approach to achieving robust, low-power perception in robotics, owing to its high temporal resolution, wide dynamic range, and low information redundancy. However, the sparse and asynchronous nature of event streams presents a significant challenge for data processing. The mainstream approach preprocesses event streams into various representations (e.g., event frames, 3D voxels) before performing subsequent operations, leading to issues such as feature loss, event stacking, and high computational burden. In this paper, we propose a fully neuromorphic system that leverages the asynchronous characteristics of event streams and spiking neural networks to enable asynchronous processing of events. Our asynchronous processing of event streams enhances robustness across different time windows and lighting conditions while significantly reducing power consumption during inference. Our fully asynchronous neuromorphic system has been validated on a real mobile robot and is expected to advance the robot perception system towards biological perception.

This brief presents a compact model to capture the major difference between high-voltage (HV) and low-voltage MOSFETs, i.e., the carrier velocity saturation effect in the drift region of HV MOSFETs. We discuss the numerical and behavioral issues that can arise in SPICE simulations with the existing current-dependent formulation in Berkeley-Short-Channel-IGFET model (BSIM) for HV transistors. We then demonstrate how a voltage-dependent formulation can mitigate them without losing simplicity and accuracy. We also validate the proposed model against experimental data of HV transistors.

Since its inception, the semiconductor industry has used a physical dimension (the minimum gate length of a transistor) as a means to gauge continuous technology advancement. This metric is all but obsolete today. As a replacement, we propose a density metric, which aims to capture how advances in semiconductor device technologies enable system-level benefits. The proposed metric can be used to gauge advances in future generations of semi-conductor technologies in a holistic way, by accounting for the progress in logic, memory, and packaging/integration technologies simultaneously.

This month’s issue offers insight into efficient compression and execution of DNNs, the challenge of connecting rural areas, and the clique problem in wireless communication. which

We study, for the first time, full chip power benefits of negative capacitance FET (NCFET) device technology for commercial-grade GDSII-level designs. Owing to sub-60mV/decade characteristics, NCFETs provide significantly higher drive-current than standard FETs at a given voltage, enabling significant iso-performance power savings by lowering VDD. We use SPICE models of NCFETs corresponding to 14nm node, which incorporate experimentally calibrated models of ferroelectric. We then characterize NCFET-based standard-cell libraries followed by full-chip NCFET-based GDSII-level design implementations of different benchmarks. Our results show that even with increased device capacitance, we can achieve about 4× (up to 74.7%) full-chip power reduction with low-VDD NCFETs over nominal VDD baseline FETs at iso-performance. The power savings are consistent across multiple benchmarks and are higher for low power designs.

We enhance the capability of industry standard compact model BSIM6 to model the parasitic current$ I_{{\text {edge}}}$at the shallow trench isolation edge. Accurate, efficient, and scalable model for$ I_{{\text {edge}}}$is developed by finding the key differences between$ I_{{\text {edge}}}$and main device drain current ($ I_{{\text {main}}}$). It is found that$ I_{{\text {edge}}}$has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to$ I_{{\text {main}}}$. These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage.

Two new MOSFET structures are candidates for sub-20nm IC technologies according to International Technology Roadmap for Semiconductors. FinFET and UTB-SOI transistors are poised to replace today' s MOSFETs and will provide much needed relief to ICs from their power and device variation predicaments.

On-chip global interconnect exhibits clear frequency dependence in both resistance (R) and inductance ( L). In this paper, its impact on modern digital and radio frequency (RF) circuit design is examined. First, a physical and compact ladder circuit model is developed to capture this behavior, which only employs frequency independent R and L elements, and thus, supports transient analysis. Using this new model we demonstrate that the use of dc values for R and L is sufficient for timing analysis (i.e., 50% delay and slew rate) in digital designs. However, RL frequency dependence is critical for the analysis of signal integrity, shield line insertion, power supply stability, and RF inductor performance.

Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations.

A novel concept of bidirectional transformation between on-chip coupling noise waveform and delay-change curve (DCC) using closed-form equations is described in this paper. These equations are targeted for use in: 1) the efficient generation of DCCs and 2) accurate experimental determination of subnanosecond coupling noise. In particular, we explore the concept of using analytical models to efficiently generate DCCs that can then be used to characterize the impact of noise on any victim/aggressor configuration. The concept is model independent, although we investigate several common noise modeling choices and perform a sensitivity analysis to optimize the generation of DCCs. By extending existing noise models, arbitrary configurations can be considered including multiple aggressors in the timing-analysis framework. Simulation using the analytical approach closely matches time-consuming SPICE simulations, making noise-aware timing analysis using DCCs both efficient and accurate. A test chip using a 0.25-/spl mu/m CMOS process was designed and its measurement results also show good agreement with SPICE simulations.

A priori interconnect prediction and technology extrapolation are closely intertwined. Interconnect predictions are at the core of technology extrapolation models of achievable system power, area density, and speed. Technology extrapolation, in turn, informs a priori interconnect prediction via models of interconnect technology and interconnect optimizations. In this paper, we address the linkage between a priori interconnect prediction and technology extrapolation in two ways. First, we describe how rapid changes in technology, as well as rapid evolution of prediction methods, require a dynamic and flexible framework for technology extrapolation. We then develop a new tool, the GSRC technology extrapolation system (GTX), which allows capture of such knowledge and rapid development of new studies. Second, we identify several "nontraditional" facets of interconnect prediction and quantify their impact on key technology extrapolations. In particular, we explore the effects of interconnect design optimizations such as shield insertion, repeater sizing and repeater staggering, as well as modeling choices for RLC interconnects.

In this paper we address both empirically and theoretically the impact of an advanced manufacturing phenomenon on the performance of high-speed digital circuits. Using data collected from an actual state-of-the-art fabrication facility, we conducted a comprehensive characterization of an advanced 0.18-/spl mu/m CMOS process. The measured data revealed a significant systematic, rather than random spatial intrachip variability of MOS gate length, leading to large circuit path delay variation. The delay of the critical path of a combinational logic block varies by as much as 17%, and the global skew is increased by 8%. Thus, a significant timing error and performance loss takes place if variability is not properly addressed. We derive a model, which allows estimating performance degradation for the given circuit and process parameters. We demonstrate explicitly that intrachip Lgate variation has a significant detrimental impact on the overall circuit performance, shifting the entire distribution of clock frequencies toward slower values. This is in striking contrast to the impact of interchip Lgate variation, traditionally considered in statistical circuit analysis, which leads to the variation of chip clock frequencies around the average value. Moreover, analysis shows that the spatial, rather than proximity-dependent systematic Lgate variability, is the main cause of large circuit speed degradation. The degradation is worse for the circuits with a larger number of critical paths and shorter average logic depth. We propose a location-dependent timing analysis methodology that allows mitigation of the detrimental effects of Lgate variability and have developed a tool linking the layout-dependent spatial information to circuit analysis. We discuss the details of practical implementation of the methodology, and provide guidelines for managing design complexity.

/sup A/ new approach to handle inductance effects for multiple signal lines is presented. The worst-case switching pattern is first identified. Then a numerical approach is used to model the effective loop inductance (L/sub eff/) for multiple lines. Based on a look-up table for L/sub eff/, an equivalent single line model can be generated to decouple a specific signal line from the others to perform static timing analysis. Compared to the use of full RLC netlists for multiple lines, this approach greatly improves the computational efficiency and maintains accuracy for timing and signal integrity analysis. We apply these models to repeater insertion in critical paths and find that, for a single line, the RLC model minimizes delay with fewer number of repeaters than RC model. However, for multiple lines, we find that same number of repeaters is inserted for optimal delay according to both the RC and RLC models.

In this paper, we quantify the impact of global interconnect optimization techniques that address such design objectives as delay, peak noise, delay uncertainty due to noise, power, and cost. In doing so, we develop a new system-performance simulation model as a set of studies within the MARCO GSRC Technology Extrapolation (GTX) system. We model a typical point-to-point global interconnect and focus on accurate assessment of both circuit and design technology with respect to such issues as inductance, signal line shielding, dynamic delay, buffer placement uncertainty and repeater staggering. We demonstrate, for example, that optimal wire sizing models need to consider inductive effects-and that use of more accurate (-1,3) worst-case capacitive coupling noise switch factors substantially increases peak noise estimates compared to traditional (0,2) bounds. We also find that optimal repeater sizes are significantly smaller than conventional models would suggest, especially when considering energy-delay issues.

Using data collected from an actual state-of-the-art fabrication facility, we conducted a comprehensive characterization of an advanced 0.18 /spl mu/m CMOS process. The measured data revealed significant systematic, rather than random, spatial intra-chip variability of MOS gate length, leading to large circuit path delay variation. The critical path value of a combinational logic block varies by as much as 17%, and the global skew is increased by 8%. Thus, a significant timing error (/spl sim/25%) and performance loss takes place if variability is not properly addressed. We derive a model, which allows estimating performance degradation for the given circuit and process parameters. Analysis shows that the spatial, rather than proximity-dependent, systematic Lgate variability is the main cause of large circuit speed degradation. The degradation is worse for the circuits with a larger number of critical paths and shorter average logic depth. We propose a location-dependent timing analysis methodology that allows to mitigate the detrimental effects of Lgate variability, and developed a tool linking the layout-dependent spatial information to circuit analysis. We discuss the details of the practical implementation of the methodology, and provide the guidelines for managing the design complexity.

Article Free Access Share on On thermal effects in deep sub-micron VLSI interconnects Authors: Kaustav Banerjee Integrated Systems, Department of Electrical Engineering, Stanford University, Stanford, CA and Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA Integrated Systems, Department of Electrical Engineering, Stanford University, Stanford, CA and Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CAView Profile , Amit Mehrotra Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CAView Profile , Alberto Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CAView Profile , Chenming Hu Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CAView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999Pages 885–891https://doi.org/10.1145/309847.310093Published:01 June 1999Publication History 60citation1,225DownloadsMetricsTotal Citations60Total Downloads1,225Last 12 Months111Last 6 weeks22 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Publisher SiteeReaderPDF

A statistical performance simulation (SPS) methodology for VLSI circuits is presented. Traditional methods of worst-case corner analysis lack accuracy and Monte-Carlo simulations cannot be applied to VLSI circuits because of their complexity. SPS methodology is accurate because no statistical information about the device parameter variation is lost. It achieves efficiency by analyzing the smaller circuit blocks and generating the performance distribution for the entire circuit. Circuit evaluation at any specified performance level is possible.

In this paper, we present a simple and accurate MOSFET channel charge model for device modeling in circuit simulation. The model can guarantee good continuities and smooth transitions of charge, capacitance, current, and transconductance from subthreshold to strong inversion with a unified analytical expression, and agrees with the experimental data well at various process and bias conditions from subthreshold and strong inversion, including the moderate inversion region of growing importance for low-voltage/power circuits.

Article Free Access Share on Device and technology optimizations for low power design in deep sub-micron regime Authors: Kai Chen 211-72 Cory Hall, E.E.C.S. Department, University of California at Berkeley, Berkeley, CA 211-72 Cory Hall, E.E.C.S. Department, University of California at Berkeley, Berkeley, CAView Profile , Chenming Hu 211-72 Cory Hall, E.E.C.S. Department, University of California at Berkeley, Berkeley, CA 211-72 Cory Hall, E.E.C.S. Department, University of California at Berkeley, Berkeley, CAView Profile Authors Info & Claims ISLPED '97: Proceedings of the 1997 international symposium on Low power electronics and designAugust 1997 Pages 312–316https://doi.org/10.1145/263272.263363Published:01 August 1997Publication History 4citation108DownloadsMetricsTotal Citations4Total Downloads108Last 12 Months6Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Accurate MOSFET I/sub dsat/ model including LDD parasitic resistance and channel subthreshold leakage models current MOSFET operation regions, particularly moderate inversion and subthreshold regions that are important for low power electronics, have been presented with measurement data. Based on these accurate models, CMOS gate performance and power consumption optimization guidelines have been discussed in terms of device T/sub ox/, V/sub dd/ and V/sub t/. It predicts that there exists certain T/sub ox/ value that can minimize the gate delay. Device designs for low power electronics considering trade-offs by varying V/sub dd/, T/sub ox/ and V/sub t/ are highlighted.

The goals and constraints of MOSFET scaling are reviewed, and the role of reliability constraints is highlighted. It is concluded that judicial shrinking of MOSFET device dimensions can sustain the historical trend of scaling through the 0.09- mu m (4-Gb SRAM) generation of technology, which may be used for IC production in the year 2010. Power supply voltage reduction plus the desire for large transistor current will create a demand for ever thinner gate oxides that can withstand ever higher electric field. Built-in reliability must replace the traditional end-of-the-line reliability testing for future complex circuits. Circuit reliability simulation may be one of the necessary tools for achieving built-in reliability.>

Berkeley reliability tools (BERT) simulates the circuit degradation (drift) due to hot-electron degradation in MOSFETs and bipolar transistors and predicts circuit failure rates due to oxide breakdown and electromigration in CMOS, bipolar, and BiCMOS circuits. With the increasing importance of reliability in today's and future technology, a reliability simulator such as this is expected to serve as the engine of design-for-reliability in a building-in-reliability paradigm. BERT works in conjunction with a circuit simulator such as SPICE in order to simulate reliability for actual circuits, and, like SPICE, acts as an interactive tool for design. BERT is introduced and the current work being done is summarized. BERT is used to study the reliability of a BiCMOS inverter chain, and performance data are presented.>

Based on an approximate solution to the nonlinear current continuity equation in the channel, an analytic non-quasi-static model for long-channel MOSFETs has been derived and implemented in SPICE. The model includes the large-signal transient and the small-signal AC analyses, although only the AC model is reported. Excellent agreement in simulation results has been achieved between this work and CODECS (a mixed device and circuit simulator). The CPU time required for this work is about twice as long as that for currently available quasi-static MOSFET models in SPICE.>

An analytic charge sheet capacitance model for short-channel MOSFETs is derived and implemented in SPICE. It is based on a surface potential formulation which computes the approximate surface potential without iterations. The DC current, charges, and their first and second derivatives are continuous under all operating regions. Equations for node charges are derived to guarantee charge conservation. Short-channel effects such as velocity saturation, channel-length modulation, and channel-side-fringing-field capacitances are included in the model equations. The model shows good agreement with the measured gate capacitance for long- and short-channel MOSFETs. The SPICE simulation of a ring oscillator using this model shows the significant variation of circuit performance due to the short-channel effects on capacitances.>

An analytic charge-conserving non-quasi-static (NQS) model is derived for long-channel MOSFETs and has been implemented in SPICE3. The model is based on approximate solutions to the transient current continuity equation, an analytic equations are derived for node charges using the charge-sheet formulation. The NQS effects in several test circuits, which include a pass transistor, a CMOS inverter chain, and a differential sample-hold circuit, are stimulated. Excellent agreements have been observed among this work, PISCES (2-D device simulation), the 1-D numerical simulation, the multiple lump model, and CODECS (a mixed device and circuit simulation). However, large differences have been observed between this work and conventional quasi-static (QS) models. The model computation time of this work implemented in SPICE3 is about 2-3 times larger than those of QS models (BSIM, Level-2 Meyer) in SPICE3.>

Reliability issues affecting MOS and bipolar ICs are reviewed. Hot-carrier-induced degradation of MOS and bipolar circuits are used to illustrate the potential role of reliability CAD tools. Electromigration lifetimes under pulse DC and AC current stressing are longer than previously thought. Oxide breakdown offers a case study for accelerated test modeling, defect statistics, and burn-in optimization.>