This paper describes scale-recursive symbol constellations for the synchronous multiple-access (MA) channel, which can be seen as a generalization of Voronoi coding. The constellations are related by a fixed scaling and rotation, and are designed so that in the noise-free case, the combined signal always falls onto an appropriate lattice. This allows high throughput and a linear complexity decoding algorithm. Novel constellations of up to 24 dimensions are given that show improved performance over conventional rectangular lattices.

In this paper, the problem of finding good wordlength combinations for fixed-point digital signal processing flowgraphs is addressed. By formulating and solving an approximate optimization problem, an estimated Pareto-optimal curve for attainable cost/quality combinations is rapidly calculated. This curve and the associated wordlength combinations are useful in several situations and can serve as starting points for real design searches. Examples that illustrate these concepts are given.

In many geometric estimation problems, we must recover sets of unit-norm direction vectors from noise-contaminated inner product observations. This article shows (1) an approximate least squares recovery method similar to the algebraic constant modulus algorithm and (2) a direct application to direction finding with a sensor array of unknown geometry using time delay of arrival data.

This paper concerns an efficient algorithm for the solution of the exterior orientation problem. Orthogonal decompositions are used to first isolate the unknown depths of feature points in the camera reference frame, allowing the problem to be reduced to an absolute orientation with scale problem, which is solved using the singular value decomposition (SVD). The key feature of this approach is the low computational cost compared to existing approaches.

Our team is developing an integrated algorithm analysis and mapping environment for migrating a dataflow representation of a signal processing algorithm into an Adaptive Computing System (ACS) consisting of FPGAs. This environment allows designers to transform signal processing algorithms into FPGA-based hardware faster, by an order of magnitude, than is currently possible. Our approach has been to focus on three areas of capability critical to the success of adaptive computing: algorithm analysis, algorithm mapping, and smart generators. These capabilities are being implemented as extensions to the Ptolemy design environment developed at the University of California, Berkeley (http://ptolemy.cecs.berkeley.edu). Our tools were used to automatically implement a Winograd DFT and a high speed linear FM detector. In both cases, our tools simulated the algorithm, selected appropriate fixed point representations, and generated the VHDL implementations. The final FPGA designs were obtained by synthesizing the VHDL and performing place and route with commercial tools.

The use of multiple images to perform scene reconstruction and camera position and orientation recovery is of practical importance for many computer vision tasks. This paper describes a fast and approximate batch algorithm for the determination of multiple camera positions and orientations from feature point data. The singular value decomposition is used extensively, providing a fast motion recovery method that avoids the iterative optimization procedures common to multiframe motion recovery approaches.

We are developing an integrated algorithm analysis and mapping environment particularly tailored for signal processing applications on Adaptive Computing Systems (ACS). Our environment allows a designer to map signal processing algorithms to an ACS faster, by an order of magnitude, than is currently possible.

FPGA and configurable computing-based DSP algorithms have demonstrated significant performance improvements over software implementations. This has caused renewed interest in developing or mapping DSP algorithms to custom hardware. An algorithm will be successfully mapped if the intermediate wordlengths can be reduced to maintain reasonable hardware size. We consider linear hardware cost functions, for which we can derive closed-form expressions for the reduced wordlengths. We then apply these results to an adaptive LMS filter, where we adapt not only the tap weights, but also the wordlengths as a function of the data in real-time.

A recent paper describes the use of Svoboda's binary counter in the construction of fast parallel multipliers. The resulting approach was shown to be faster than the conventional Dadda multiplier when the wordlength N was small. Unfortunately, the growth in the number of gates of that method was O(N/sup 3/) and the speed was O(N). In this paper, Batcher's bitonic sorting network and other efficient networks replace the Svoboda counter. The asymptotic growth rate in gates of these new methods is O(N/sup 2/ log/sup 2/ N), and the speed is O(log/sup 2/ N).

The performance of Hausdorff distance-based clutter/target discrimination is characterized. This allows selection of detection thresholds and pre-processing parameters to achieve the desired detection performance. An efficient systolic array implementation of Hausdorff distance-based target/clutter discrimination is presented.

Techniques that estimate frequency and chirp rate as weighted sums of phase differences have received attention because they can be simple to implement. The novel contributions in this paper include the efficient implementation of these estimates through recursive structuring of the computation and trapezoidal approximation of the weighting functions. A multirate cascade structure for the trapezoidal weighting is given that allows frequency and chirp rate estimates to be formed for multiple analysis window lengths with little extra computation. The techniques described are particularly well suited to hardware implementation because they virtually eliminate multiplications while having little impact on performance.

We address the design of hardware-efficient digital implementations for the estimation of sinusoidal frequency from noisy data. We are motivated by the design of digital microwave receivers with high sample rates, which thus require simple processing to be cost-effective. By a controlled introduction of potential ambiguities and by use of formulas for the noise-free Prony (1795), or linear prediction coefficients, we provide several novel approaches to simple, effective frequency estimation.

Image registration is an important task in matching two or more images with unknown rotation, displacement, and scaling. A class of registration algorithms uses the location of feature points in the images, rather than pixel intensity values to perform the registration. An O(N/sup 3/) algorithm of this type that uses both relative distance and angle information is examined. The algorithm allows for missing and spurious feature points, and can provide scale mismatch information. It requires less computation than a previous method.

Rapid prototyping is well suited to address the signal processing design tasks encountered an research applications. The applications differ from defence or industrial applications in that the signal processing requirements are either evolving or poorly understood. In the field of underwater acoustic (UWA) communications, practical solutions, and thus their implementations, are still maturing. Sanders and WHOI are using the development of an improved UWA modem to exercise the processes and environments being developed at Sanders under the RASSP program. We provide an overview of the signal processing requirements for UWA communications. We outline the impact of these requirements on system design and describe the application of RASSP processes to system architecture specification. Finally, several potential paths for future development are described, both for system upgrades and for new applications.

This paper presents two case studies of the rapid development of military signal processors and a description of how the experiences learned on these programs are being leveraged into an ARPA/Tri-Service initiative. The two case studies emphasize end-to-end system simulation and the use of rapid prototyping tools and special hardware for rapid development. Rapid Prototyping of Application Specific Signal Processors, or RASSP, is an initiative to create a new process for the development of military signal processors. The objective of RASSP is to specify a process which both reduces the development time and the cost of military signal processing systems while improving their quality and their long term supportability. RASSP processors are meant to be incrementally upgradable over long development and life cycles. While RASSP represents a significantly harder problem than the two examples described here, the lessons learned in these examples are being incorporated in the RASSP approach.>