Given the exponential increase of fabrication costs, the global recession and credit crunch, one may ask if Moore's Law is financially viable beyond 22nm node. Can we justify the return-of-investment (ROI) for continuous scaling beyond 22nm? Shall we consider other alternatives for integration, such as silicon-in-a-package (SiP) or 3D integrations?

DFM has taken shape by virtue of manufacturers defining a series of "DFM activities", related to parametric and stochastic yield analysis and recommendations for design changes to improve yield. The picture is made more complex because the view from integrated device manufacturers, pure play foundries, and fabless semiconductor companies is not necessarily the same as they have different needs and constrains. This panel brings together DFM practitioners from each of these communities to discuss real experiences on the adoption level achieved so far as well as the impact in the manufactured products. The panel should be of interest of designers moving to advanced nodes (to learn from the experience of those that have "done it already") as well as those in the leading edge (such that they can compare experiences).

Historically, Back End of Line (BEOL) or interconnect resistance and capacitance have been viewed as parasitic components. They have now become key parameters with significant impact on circuit performance and signal integrity. This paper examines the types of BEOL variations and their impact on RC extraction. The importance of modeling systematic effects in RC extraction is discussed. The need for minimizing the computational error in RC extraction before incorporating random process variations is emphasized.

Design of reliable chips with high yield is an extremely challenging task in UDSM technologies. Time to market pressures, which often limit the necessary verification before tape-out, typically are manifested as ramp-to-production problems on “good” designs either in the manufacturing process or in the field. Burn-in process, a reactive measure to ship reliable chips, is not effective for high volume designs. Another cause for concern is hidden failures that go undetected due to incompleteness of test vectors.

It is commonly thought that sweep-back effects would make electromigration (EM) a non-issue in signal lines. However this is only the case when the shape of the positive and negative current pulses are closely matched. Moreover, as performance pressures increase, the peak current values are exceeding the range for which electromigration models are valid. Thus, during the design of TI's TMS320c6201 DSP chip, it was determined that limits needed to be placed on the current densities in signal-line segments, and that every net in the design should be checked. Dynamic current density analysis on all nets of a large design is computationally very expensive. In this paper, we describe a practical CAD methodology for a static, signal electromigration analysis for large cell-based designs. We present results and some observations from application of this methodology on the TMS320c6201.

As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of digital VLSI chips. Are functional failures due to noise really a problem in a static CMOS design? Are design rules in the circuits and interconnect sufficient to protect against noise failures? Do design rules targetted to ensure noise immunity result in excessive penalty to performance and area due to their inherent conservatism? Is inductance in the interconnect really a problem? How much do we really need to account for capacitive coupling inductance, and inductive coupling in delay analysis?

Thispaperpresents the descrtption of the architecture of the Chip Hierarchical Design System (CHDS) and details on the requiredTiming Driven Physical Design capabilities that have been defined to satisfy the physical design needs for 0.234 technologies and beyond.These requirements are intended to solve the challenges including the Design Productivity Crisis identijed by semiconductor industry, the shi$ in the design paradigm where the timing of a physical design will be dominated by interconnect effects, and the need for an integrated physicar design system which still supports "plug-and-play" through the use of EDA standard languages, moak's, and inte$aces.

Fast and efficient computation of signal characteristics such as delay, slew etc. play a key role in design and analysis of high performance VLSI circuits. Elmore approximation may not be accurate when resistive components of the interconnect significantly affect signal characteristics. An efficient mechanism to compute the driving point admittance of a resistive interconnect tree exists, in which the tree is traversed bottom-up to compute the driving point admittance (DPA). An approximation technique is proposed in this paper which involves traversing an interconnect RC tree top-down to compute the signal characteristics, by exploiting already calculated admittance at every node. A piecewise linear approximation obtained from the analytical expression for voltage at every node is used to compute voltages at subsequent nodes in the tree. The advantage of the proposed technique is efficient and fast computation of interconnect signal characteristics from already computed admittance information. Results comparing the proposed technique with RICE and Elmore on representative RC trees of antifuse based FPGA interconnect are presented.>

Article A new optimizer for performance optimization of analog integrated circuits Share on Author: N. S. Nagaraj View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 148–153https://doi.org/10.1145/157485.164643Published:01 July 1993 3citation205DownloadsMetricsTotal Citations3Total Downloads205Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access