This study developed an application-specific integrated circuit (ASIC) with a speed controller, a nine-stage error fuzzy controller, and a discrete multiple vector voltage (DMVV) system for modified direct torque control (MDTC). By using the nine-stage error fuzzy controller, the proposed system effectively stabilizes a motor’s flux and ensures high control precision by incorporating speed feedback. This feature enables the system to ensure that the flux and torque values are close to the designed values, which results in high motor performance. A DMVV switching table plays a crucial role in facilitating the appropriate six-switch signals on the basis of the modified flux and torque signals from the fuzzy controller. The proposed DMVV system considerably reduces ripples and enhances overall system stability by generating more vector voltages than those generated in the conventional DTC method. The proposed system architecture and functional modules were implemented using Verilog hardware description language. After the syntax and functionality of the designed ASIC were rigorously verified using a field-programmable gate array development board, the designed ASIC was fabricated through the 0.18-μm complementary metal–oxide–semiconductor process of Taiwan Semiconductor Manufacturing Company. This ASIC caters to the specific requirements of three-phase induction motors. Measurement results indicated that the fabricated ASIC had a chip area of 0.974 × 0.976 mm2, a sampling frequency of 40 MHz, and power consumption of 0.5957 mW under a supply voltage of 1.8 V and an operating frequency of 10 MHz.

An 8-tap feed-forward equalizer (FFE) and 10-tap decision feedback equalizer (DFE) were designed for the IEEE 802.3u 100Base-TX specification. The weights of these adaptive filters are updated with a sign–sign least-mean-square (SSLMS) algorithm. To ensure the flexibility of the circuits for various environments channel lengths, the equalizers are designed such that the number of taps can be adjusted to between 1 and 8 for the FFE and 1 and 10 for the DFE. Results indicated that the equalizer can compensate for channel delays of more than 20 dB, and it achieved a bit error rate of 2 × 10−3. Both FFE and DFE not only mitigate signal distortion but also significantly eliminate inter-symbol interference (ISI) in high-speed serializer/deserializer (SerDes) communication systems. The application-specific integrated circuit (ASIC) was designed using Verilog Hardware Description Language (HDL) and implemented with the TSMC 90-nm CMOS 1P9M standard cell process. In simulations, the chip area, delay cycle, and logic gate counts were 845.445 × 845.445 μm2, 12 cycles, and 75 187 gates, respectively. The supplied voltage and frequency of the proposed adaptive DFE were 1.2 V and 250 MHz, respectively.

This study proposes a direct torque control (DTC) application-specific integrated circuit (ASIC) equipped with a neural network and a fuzzy hysteresis controller to achieve seamless control of a three-phase induction motor. In the proposed DTC system, feedback currents and voltages measured at the stator are fed into the hysteresis controller and a switching table. Subsequently, six-arm voltages are generated based on the voltage vector selector table to drive the RM5G inverter. However, severe switching noise is present in the power transistors of the inverter. These problems lead to numerous large ripples, instability, and delayed torque and flux responses at the stator. To address the aforementioned challenges, this study proposes a fuzzy controller to enhance flux signals. This controller incorporates a fuzzifier, a fuzzy rule base, and a defuzzifier. Additionally, a backpropagation neural network control is employed to improve torque signals. The multilayer neural network is utilized not only to calculate torque rapidly but also to enhance calculation accuracy. The proposed control method effectively reduces flux and torque errors, facilitating smooth control of the three-phase induction motor. After functional verification on an FPGA board, the proposed design is implemented on an ASIC fabricated using the TSMC$0.18-\mu \mathrm{m}$CMOS process. The results indicate a chip area of approximately$0.959\times 0.9584\text{mm}^{2}$and a power consumption of 2.2524 mW at a supply voltage of 1.8 V and an operating frequency of 10 MHz.

This study proposes an Internet of Things (IoT)-based smart home system that sends and receives packets through the RS232 protocol and processes them using deep learning. A Field-Programmable Gate Array (FPGA) development board serves as a transceiver, operating a universal serial bus (USB) interface and a Wi-Fi module. The proposed system comprises a built-in wireless transceiver, a set of sensors, a development board running a deep learning algorithm, an MQTT communication protocol, and a terminal device controller. The objective is to implement an IoT -based smart home system with wireless data transmission. Node-RED is used to develop a comprehensive smart home system on the server side for IoT applications, facilitating data access, data processing, and terminal device control. The aim is to achieve automatic regulation and ensure comfortable indoor temperatures. In experiments, the root mean squared error difference between actual and predicted temperatures was approximately 0.4426 °C. After evaluation experiments with the FPGA development board, an application-specific integrated circuit (ASIC) based on the TSMC 0.18-μm CMOS process was used. Simulation results indicate that the chip area is approximately 1.186 × 1.188 mm2, and the dynamic power consumption is approximately 8.1674 mW at a power supply of 1.8 V and operating frequencies of 50 and 5 MHz.

In this study, we propose a modified predictive direct torque control (PDTC) application-specific integrated circuit (ASIC), comprising a neural network (NN) proportional integral derivative (PID) controller, speed-sensorless control, fuzzy error controller, and seven-stage hysteresis controller, to alleviate the ripple problem induced by limited vector voltages and slow speed response in conventional direct torque control. Both flux and torque errors pass through the modified discrete multiple vector voltage switch table to obtain the required vector voltages, and the proposed NN PID controller is used to convert the speed error into a torque command. Notably, the motor speed is evaluated from the magnetic flux, which is calculated using two-phase currents and voltages. The speed-sensorless control not only accelerates the feedback control but also rotates more stably. The NN PID controller generates a torque command according to the speed error, which is obtained by subtracting the estimated predictive speed from the actual speed. The advantages of the proposed system are that it reduces the flux and torque ripples and increases the control stability by filtering out the external interferences. The Verilog hardware description language is used to implement the proposed PDTC ASIC system, and a field-programmable gate array development board is used to verify the designed functions.

This paper presents an Ethernet packet transformation and transmission architecture between Modbus transmission control protocol (Modbus/TCP) and universal serial bus (USB) 3.0 developed with a field-programmable gate array (FPGA) development board. The proposed architecture is used to complete packet transformation and transmission between Ethernet and USB 3.0 for application in plant automation. The Ethernet receiver receives and analyzes Modbus/TCP packets and sends the source address, destination address, IP header, and Modbus/TCP header to the register to verify the correctness of the packet. The Modbus/TCP packet is stored in static random access memory and awaits access by a USB 3.0 module. An FPGA development board (Intel DE10-Standard) is used for functional verification. The measured results show that the latency, throughput, and dynamic power are 18.845 ×s, 747.45 Mbps, and 142.17 mW, respectively, at a voltage of 1.8 V and operating frequency of 125 MHz.

This paper presents the packet processing and transmission of a field programmable gate array (FPGA) development board by using an RS-485 interface module and Verilog HDL. The proposed communication protocol was established between the sensors in the sensing layer and web server. In the sensing layer, the sensor system, which comprises a temperature sensor, warning light, and fan, controls the environment temperature. An attractive Internet of Things application system was proposed to simultaneously monitor real-time temperature information through wireless communication and the webpage. Node-RED software was used to develop the home care system because of its advantages in facilitating management and maintenance. The linkage function was written in the JavaScript language on Node-RED software. In the designed system, when the temperature reaches the preset value, the fan and warning light automatically turn on and a notification email is sent to the user. The measurement results showed that the throughput and conversion time were 0.00958 Mbps and 283.83 ms, respectively, at a clock frequency of 1 MHz and Baud rate of 9600 bps.

In this paper, the authors propose a smart home-care system built on an Android smartphone. The database and application programming interface (API) are set up on the server side. The database collects information from various sensors and stores it, and the API acts as a bridge between the mobile phone and the database. The API prevents the leakage of private data. In the associated Android smartphone app, two functions are provided: instant monitoring based on in-home sensor data and fall detection using the three-axis accelerometer, gyroscope, and orientation sensor inbuilt into the smartphone. When the sensor data are abnormal, the remote controller is notified immediately. Moreover, the remote controller can view real-time images by using an IP camera to guarantee home safety. As for fall detection, given that falls cause severe injuries in elder people and children, the proposed app can detect a fall event, send a help message, and indicate the user's location by using the global positioning system and Google Maps API. According to the simulation results obtained in this study, the proposed system exhibited a fall-detection sensitivity of 92.5% and specificity of 97.6%, thus proving that the system can be effectively used for home care.

This paper proposes the adaptive functional coupling recurrent cerebellar model articulation controller (AFCRC). The AFCRC system contains an integrated error function, a TSK fuzzy compensator, and a novel cerebellar model articulation controller (CMAC), which is developed based on the concept of a recurrent neural networks (RNNs) and a functional coupling NN (FCNN). This study uses the proposed AFCRC to control the direct torque control drive system of a switched reluctance motor (SRM), and compares it with the traditional CMAC and FCMAC. The experimental results reveal that the root mean square error (RMSE) is used as a performance index for comparing of the traditional CMAC, FCMAC, and AFCRC, respectively. The results show that the proposed AFCRC exhibits the robustness against external disturbances. Thus, the proposed control strategy is advantageous at various speed commands and has improved dynamic responses.

This paper presents an intelligent packet transmission system between an Ethernet and a synchronous optical network involving format transformation based on a field-programmable gate array (FPGA) development board. Client data are fed to the RS485 port on the FPGA board (Tx) and then transformed into an Ethernet packet. The E/O converter (Tx) converts an electrical signal to an optical signal and transmits it through the optical fiber to the receiver. The O/E converter (Rx) converts an optical signal to an electrical signal, which is captured using the FPGA board. The signal is then sent to the client through the RS485 port. The client terminal can display the received data to verify the transceiver function. Optical fiber transmission has properties such as high speed, long distance, and low interference, whereas electrical transmission does not possess these features. The intelligent packet transformation and transmission mechanisms were implemented using the Verilog hardware description language and verified through the FPGA development board on the RS485 serial port. The measured results indicated that the operational frequency, data transfer rate of the RS485 port, power consumption, and chip size were 125 MHz, 115,200 bps, 137 mW, and 1.27 × 1.27 mm2, respectively, at a data volume of 8 bits and a first-in-first-out queue of 1K bytes.

This paper presents a modified direct torque control (MDTC) application-specific integrated circuit (ASIC), which includes a proportional-integral-derivative (PID) speed controller and five-stage fuzzy hysteresis, for reducing torque and flux ripples, which are induced by the low vector voltage and slow response speed of the traditional DTC circuit. The high-speed fuzzy PID controller and five-stage fuzzy hysteresis improve control stability. The proposed PID controller reduces the flux and torque ripples through the modified discrete multiple vector voltage (MDMVV). The proposed MDTC ASIC not only reduces torque and flux ripples but also enhances the stability of the control system. The proposed MDMVV generates four voltage vectors in a sampling cycle, whereas the conventional DTC generates a single voltage vector. Hardware description language was used to design and implement the motor control, and a programmable logic gate array board was used to verify the designed functions. The MDTC ASIC was fabricated using the 0.18-μm CMOS process with a chip area of 1.193 × 1.190 mm2. At an operating frequency of 10 MHz and a voltage of 1.8 V, the power consumption was determined to be 2.457 mW.

The data transmission is fairly quick and easy in recent years. Nowadays, there are many serial data transmission methods, such as I2C, SPI, RS-232, USB (Universal Serial Bus), and so on. Recently, USB not only works with convenience but also transmits data fast. It becomes a standard peripheral interface between FPGA development board and personal computer (PC). To satisfy those requirements, the data transmission speed and data volume of USB physical transceiver are continuously improved. The transmitted data will be queued with first-in first-out register (FIFO), proceeding with serial interface engine (SIE), compiling with the USB packet format, and converting it into an analog differential signal by using the Cypress's USB PHY (Port Physical Layer) chip. Then the USB packet will be sent from the transmitted FPGA board to the received FPGA board through the USB cable. Two FPGA boards with USB PHY are used to verify the transceiver function. After the functional verification has been completed, an application-specific integrated circuit (ASIC) of FIFO and SIE are implemented with TSMC 0.18μm CMOS technology. The gate counts, power consumption, operating frequency, and chip area are 14,547, 2.6742 mW, 50 MHz, and 0.7×0.67 mm2, respectively, at the supply voltage of 1.8 V and the total pins of 40 pins.

This paper presents an optical transceiver, whose packet process is completed with deficit round robin (DRR) and RS232 interface, for optical synchronous optical networking (SONET) which can service on both asymmetric digital subscriber line (ADSL) and optical packet switching (OPS). To resolve the clock jitter, not only the cycle decision but also the reset function are used to synchronize the clock waveform. In the proposed DRR, it performs the packet process with low delay and low loss. Moreover, the RS232 interface, which is integrated with the field-programmable gate array (FPGA) board, is adopted due to its easy implementation. The processing data will be queued with DRR and be sent to electrical/optical (E/O) converter from the RS232 port on FPGA board (Transmitter). Passing through the optical fiber, the packet from transmitter is sent to the O/E converter and then received at the RS232 port on another FPGA board. The received electrical packet will be displayed on the seven-segment display of FPGA board to verify the transceiver function for SONET. Note that the proposed architecture is designed with Verilog hardware describe language (Verilog HDL). According to the measured results, the data transfer rate is 115,200 bps with the FPGA operating frequency of 50 MHz and the fiber distance of 5 km.

This paper presents a predictive direct torque control (PDTC) system with discrete multiple vector voltage (DMVV) and fuzzy hysteresis for a three-phase induction motor. A fuzzy hysteresis controller is proposed to establish a DMVV for estimating both flux and torque errors, which are the membership functions of the fuzzy system. DMVV switching timing ensures that an appropriate voltage vector is sent to the inverter. The difference between conventional switching timing and DMVV is that conventional timing produces a stator voltage vector in a cycle, whereas DMVV produces four stator voltage vectors in a cycle. The proposed DMVV not only reduces the ripples that are generated with sampling errors and delays, but also enhances the stability of the PDTC system. Verilog hardware description language is used to implement the hardware architecture; a field programmable gate array (FPGA) development board is used to verify designed functions. According to the results measured using the FPGA development board, the proposed PDTC with DMVV and fuzzy hysteresis successfully works at an operating frequency of 50 MHz, with a supplied voltage of 1.8 V and a power consumption of 300 mW.

This paper presents a packet process with deficit round robin (DRR) ASIC, which is used not only to give up the first-in first-out (FIFO) mechanism in ATM/Ethernet bridge, but also to integrate with UTOPIA (Universal Test and Operations PHY Interface for ATM) interface between ATM Cell and Ethernet packet. Usually, the packet presents with different weight in the DRR queue. The higher the weight is, the higher the priority is to transmit packet. The proposed DRR ASIC completes the packet process with low delay and low loss. The Alter a DE3 of FPGA (Field Programmable Gate Array) is adopted to verify the designed function, and that the TSMC 0.18μm CMOS technology is used to implement the DRR ASIC after completing the design process, which includes the Synthesis, DFT (Design For Testability), APR (Auto Place and Route) DRC (Design Rule Check) and LVS (Layout Versus Schematic). According to the simulation results, the proposed ASIC performs with the gate count of 31,948 and the power consumption of 8.48 mW.

This paper presents a deficit round robin (DRR) application specific integrated circuit (ASIC), which is fabricated in a standard TSMC 0.18μm 1P6M technology. The proposed DRR ASIC not only replaces the first-in-first-out (FIFO) queue with DRR, but also improves the performance of ATM/Ethernet bridge with a fair queue in very-high-bit-rate digital subscriber line (VDSL). In the proposed DRR queue, two data formats, 4-bit and 8-bit widths, are studied. Notify that the average waiting time increases if the input queue works with small data format. According to the simulation result, the proposed DRR ASIC performs with the fault coverage of 99.5 % and the logic elements of 5,978 at the operating frequency of 50 MHz, the supplied voltage of 1.8 V and the power consumption of 90.1 mW; and that the chip area of the proposed DRR ASIC is 1.2×1.2 mm2involving pads.

This paper presents a modified predictive direct torque control (PDTC) application specific integrated circuit (ASIC) with speed feedback controller in motor drive. The proposed PDTC ASIC not only decreases the ripple of hysteresis controller but also enhances the performance of motor controller. Verilog hardware description language (Verilog HDL) is used to implement the hardware architecture; and that an ASIC is fabricated in TSMC 0.18µm process with cell-based design method. Both switching and calculating delay times mainly contribute the ripples which degrade the control quality in motor drive. By using the predictive scheme, we not only improve the ripple issue of the traditional direct torque control technique, but also make the control system more stable by decreasing the time delay in hysteresis controller. According to the measured results, the proposed PDTC ASIC performs with the coverage of 99.10 % and the fault coverage of 98.28 % at the operating frequency of 50 MHz, the supplied voltage of 1.8 V and the power consumption of 218.7 mW.

This paper presents a fuzzy direct torque control (Fuzzy-DTC) IC, which is fabricated in a standard TSMC 0.18-μm 1P6M CMOS process. The proposed chip enhances the performance of the three-phase induction motor by reducing the variations of torque and flux with fuzzy theory. In general, the motor control system firstly calculates the stator's magnetic flux and torque by detecting the current, voltage, and rotor speed of the three-phase induction motor. Using the torque error, magnetic error, fuzzy vector selection table and coordinate transformation, a suitable voltage space vector can be obtained to control the switches of MOSFET in inverter and to have a stable response in motor speed. Furthermore, the fuzzy controller and fuzzy vector selection table are used to establish an appropriate voltage vector with high operating speed and good stability. According to the simulation results, the proposed fuzzy DTC system performs with the coverage of 96.03 % and the fault coverage of 95.06 % at the operating frequency of 50 MHz, the supplied voltage of 1.8 V and the power consumption of 79.5 mW, and that the chip area of the proposed fuzzy DTC ASIC is 1.8x1.8 mm2involving pads.