VLDB 2026 Research / reviewers in the wild / expert
Luigi Rizzo
dblp:27/3297
· DBLP profile ↗
34ranked-venue papers
12as first author
6since 2021 · last 2026
0000-0003-2483-1565ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 18 · 9 first-author · 1 since 2021Systems, architecture and hardware · 8 · 2 first-author · 2 since 2021Software engineering, systems software and programming languages · 4 · 2 since 2021Artificial intelligence and machine learning · 1Applied, interdisciplinary, general and emerging computing · 1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | ATM-SB: An indoor temperature prediction approach for smart buildings based on deep learningabstractIn recent years, machine learning (ML) and deep learning (DL) have emerged as key technologies for balancing energy efficiency and thermal comfort in Internet of Things (IoT) based Smart Buildings (SBs). Among the various components of SBs, the heating, ventilation, and air conditioning (HVAC) system plays a critical role, as it significantly influences both energy consumption and occupant comfort. In this context, accurately predicting indoor temperatures is essential for optimizing HVAC operations, resulting in enhanced energy efficiency, improved comfort, and lower energy costs. To address this challenge, this paper proposes Advanced Temperature Management of Smart Building (ATM-SB), a hybrid DL approach that combines Long-Short-Term Memory (LSTM) and Gated Recurrent Unit (GRU) networks to predict indoor temperature at 15, 30, and 60 minute intervals using multivariate sensor data. Using the ATM-SB approach, a prototype was developed at AEI S.r.l., Italy. It was trained and validated on a real-world dataset collected from a smart office building and laboratory across both summer and winter seasons, and further tested on four public datasets from diverse environments. ATM-SB achieves competitive performance and demonstrates robust generalization across diverse real world and public datasets, including comparisons with LSTM, GRU, CNN-LSTM, and gradient boosting, achieving an MAE as low as 0.0098 and an R 2 of up to 0.98 on real data. Statistical validation through 5-fold cross-validation and significance testing confirms the robustness and generalization of the model. By enabling accurate forecasting across diverse scenarios, ATM-SB provides an effective solution for intelligent HVAC control in next-generation SBs. Md. Babul Islam, Antonio Guerrieri, Raffaele Gravina, Luigi Rizzo, Giuseppe Scopelliti, Vincenzo D'Agostino, Giancarlo Fortino |
Future Gener. Comput. Syst. | 4 |
| 2025 | Parallel Execution Strategies for Cellular Automata on Shared Memory ArchitecturesabstractCellular Automata (CA) are extensively utilized for modeling and simulating complex systems due to their simplicity, flexibility, and ability to represent diverse phenomena. However, the computational intensity of CA models, particularly in large-scale applications, demands the development of efficient parallel execution techniques. This is especially critical when targeting shared memory architectures, where resource management and thread coordination play pivotal roles in achieving optimal performance. In this study, we examine a range of parallel execution strategies specifically designed to enhance the efficiency and scalability of CA models. The experimental evaluation highlights good scalability in execution time and resource utilization, making these strategies highly suitable for extensive simulations across various domains. Additionally, the results emphasize that imbalance conditions—often arising during CA computations—can considerably influence the effectiveness of choosing a given strategy. Alessio De Rango, Giuseppe Mendicino, Donato D'Ambrosio, Davide Macrì, Luigi Rizzo, Rocco Rongo, William Spataro |
PDP | 6 |
| 2024 | CC-NIC: a Cache-Coherent Interface to the NICabstractEmerging interconnects make peripherals, such as the network interface controller (NIC), accessible through the processor's cache hierarchy, allowing these devices to participate in the CPU cache coherence protocol. This is a fundamental change from the separate I/O data paths and read-write transaction primitives of today's PCIe NICs. Our experiments show that the I/O data path characteristics cause NICs to prioritize CPU efficiency at the expense of inflated latency, an issue that can be mitigated by the emerging low-latency coherent interconnects. But, the coherence abstraction is not suited to current host-NIC access patterns. Applying existing signaling mechanisms and data structure layouts in a cache-coherent setting results in extraneous communication and cache retention, limiting performance. Redesigning the interface is necessary to minimize overheads and benefit from the new interactions coherence enables. This work contributes CC-NIC, a host-NIC interface design for coherent interconnects. We model CC-NIC using Intel's Ice Lake and Sapphire Rapids UPI interconnects, demonstrating the potential of optimizing for coherence. Our results show a maximum packet rate of 1.5Gpps and 980Gbps packet throughput. CC-NIC has 77% lower minimum latency, and 88% lower at 80% load, than today's PCIe NICs. We also demonstrate application-level core savings. Finally, we show that CC-NIC's benefits hold across a range of interconnect performance characteristics. Henry Schuh, Arvind Krishnamurthy, David E. Culler, Henry M. Levy, Luigi Rizzo, Samira Manabi Khan, Brent E. Stephens |
ASPLOS (1) | 5 |
| 2023 | A Review on Machine Learning for Thermal Comfort and Energy Efficiency in Smart Buildings
Md. Babul Islam, Antonio Guerrieri, Raffaele Gravina, Luigi Rizzo, Giuseppe Scopelliti, Vincenzo D'Agostino, Giancarlo Fortino |
EWSN | 4 |
| 2022 | Understanding host interconnect congestionabstractWe present evidence and characterization of host congestion in production clusters: adoption of high-bandwidth access links leading to emergence of bottlenecks within the host interconnect (NIC-to-CPU data path). We demonstrate that contention on existing IO memory management units and/or the memory subsystem can significantly reduce the available NIC-to-CPU bandwidth, resulting in hundreds of microseconds of queueing delays and eventual packet drops at hosts (even when running a state-of-the-art congestion control protocol that accounts for CPU-induced host congestion). We also discuss implications of host interconnect congestion to design of future host architecture, network stacks and network protocols. Saksham Agarwal, Rachit Agarwal 0001, Behnam Montazeri, Masoud Moshref, Khaled Elmeleegy, Luigi Rizzo, Marc de Kruijf, Gautam Kumar 0001, Sylvia Ratnasamy, David E. Culler, Amin Vahdat |
HotNets | 6 |
| 2021 | ghOSt: Fast & Flexible User-Space Delegation of Linux SchedulingabstractWe present ghOSt, our infrastructure for delegating kernel scheduling decisions to userspace code. ghOSt is designed to support the rapidly evolving needs of our data center workloads and platforms. Jack Tigar Humphries, Neel Natu, Ashwin Chaugule, Ofir Weisse, Barret Rhoden, Josh Don, Luigi Rizzo, Oleg Rombakh, Christoforos E. Kozyrakis |
SOSP | 7 |
| 2019 | BPFHV: Adaptive Network Paravirtualization for Continuous Cloud Provider EvolutionabstractCloud providers are continuously evolving their virtual networking infrastructure to improve performance and functionality. This evolution, however, typically stops at the virtual NIC interface, since any change in that domain would require impractical upgrades in the running VMs with the collaboration of the customers who own them. This could hinder many important evolutions, like the transition to newer revisions of the VirtIO standard. To overcome this problem we propose BPFHV, a new paravirtualized network meta-device that is able to dynamically change its internal operation under the hypervisor control. BPFHV comes with a set of hypervisor-provided callbacks that the guest must call to complete datapath operations, such as posting a new packet for transmission. By injecting new callbacks, the hypervisor can dynamically change the behaviour of the device and of its guest driver even after the initial deployment of a VM. We describe our prototype implementation on the QEMU hypervisor with Linux guests, reusing the eBPF infrastructure for code injection. We show some preliminary experimental results and discuss some possible further applications. Vincenzo Maffione, Giuseppe Lettieri, Luigi Rizzo |
ANCS | 3 |
| 2019 | Cache-aware design of general-purpose Single-Producer-Single-Consumer queuesabstractSummary Data processing pipelines normally use lockless Single‐Producer–Single‐Consumer (SPSC) queues to efficiently decouple their processing threads and achieve high throughput, minimizing the cost of synchronization. SPSC queues have been widely studied, mostly for applications such as streaming data or network monitoring, where the main goal is maximizing throughput. There are now many applications, such as virtual‐machine–virtual‐machine communication, software‐defined networking, and message‐based kernels, where low latency is also important, and the tradeoffs between high‐throughput and low‐latency algorithms have not been studied equally well. Furthermore, at high or variable transaction rates, the effect of memory hierarchies and cache coherence subsystems may be dominant and yield surprising results. In this paper, we make two contributions. First, we provide a comprehensive study of the two main families of SPSC queues, namely, “Lamport” and “FastForward” queues, with a detailed analytical and experimental characterization of their behavior in terms of operating regimes, throughput, latency, and cache misses. Second, we propose two new queue variants, namely, improved FastForward and batched improved FastForward, which have better worst‐case behavior than other variants in terms of cache misses, which is an important feature for a number of applications. Together, these two contributions provide practical guidelines to choose the best solution depending on the application requirements. Vincenzo Maffione, Giuseppe Lettieri, Luigi Rizzo |
Softw. Pract. Exp. | 3 |
| 2018 | A Study of I/O Performance of Virtual MachinesabstractIn this study, we investigate some counterintuitive but frequent performance issues that arise when doing high-speed networking (or I/O in general) with Virtual Machines (VMs). VMs use one or more single-producer/single-consumer systems to exchange I/O data (e.g. network packets) with their hypervisor. We show that when the producer and the consumer process packets at different rates, the high cost required for synchronization (interrupts and ‘kicks’) may reduce throughput of the system well below the slowest of the two parties; moreover, accelerating the faster party may cause the throughput to decrease. Our work provides a model for throughput, efficiency and latency of producer/consumer systems when notifications or sleeping are used as a synchronization mechanism; identifies different operating regimes depending on the operating parameters; validates the accuracy of our model against a VirtIO-based prototype, taking into account most of the details of real-world deployments; provides practical and robust strategies to maximize throughput and minimize energy while keeping the latency under control, without depending on precise timing measurements nor unreasonable assumptions on the system’s behavior. The study is particularly interesting for Network Function Virtualization deployments, where high-rate producer/consumer systems in virtualized environments are the core components. Giuseppe Lettieri, Vincenzo Maffione, Luigi Rizzo |
Comput. J. | 3 |
| 2018 | PSPAT: Software packet scheduling at hardware speedabstractTenants in a cloud environment run services, such as Virtual Network Function instantiations, that may legitimately generate millions of packets per second. The hosting platform, hence, needs robust packet scheduling mechanisms that support these rates and, at the same time, provide isolation and dependable service guarantees under all load conditions. Current hardware or software packet scheduling solutions fail to meet all these requirements, most commonly lacking on either performance or guarantees. In this paper we propose an architecture, called PSPAT to build efficient and robust software packet schedulers suitable to high speed, highly concurrent environments. PSPAT decouples clients, scheduler and device driver through lock-free mailboxes, thus removing lock contention, providing opportunities to parallelize operation, and achieving high and dependable performance even under overload. We describe the operation of our system, discuss implementation and system issues, provide analytical bounds on the service guarantees of PSPAT, and validate the behavior of its Linux implementation even at high link utilization, comparing it with current hardware and software solutions. Our prototype can make over 28 million scheduling decisions per second, and keep latency low, even with tens of concurrent clients running on a multi-core, multi-socket system. Luigi Rizzo, Paolo Valente, Giuseppe Lettieri, Vincenzo Maffione |
Comput. Commun. | 1 |
| 2016 | A Study of Speed Mismatches Between Communicating Virtual MachinesabstractThis work addresses an apparently simple but elusive problem that arises when doing high speed networking on Virtual Machines. When a VM and its peer (usually the hypervisor) process packets at different rates, the work required for synchronization (interrupts and "kicks") may reduce throughput well below the slowest of the two parties. Luigi Rizzo, Stefano Garzarella, Giuseppe Lettieri, Vincenzo Maffione |
ANCS | 1 |
| 2016 | Flexible virtual machine networking using netmap passthroughabstractThe rising interest in Network Function Virtualization (NFV) requires Virtual Machines (VMs) to operate with diversified networking workloads, from traditional, bulk TCP transfers to novel ones featuring extremely high packet rates. In response, researchers have explored and proposed new solutions for high performance VM networking, including optimizations to virtual network adapters (such as VirtIO) to support high speed bulk traffic, and alternative frameworks for userspace networking and physical or virtual passthrough. To date, we are still missing a comprehensive solution that supports such extreme workloads across multiple operating systems and hypervisors, while at the same time addressing other requirements such as ease of configuration, operating system independence, scalability and isolation. In this paper we present ptnet, an approach to network I/O virtualization that provides high performance for both traditional TCP/IP and high packet rate applications. ptnet leverages the features of the netmap framework (including virtualization and passthrough support), and defines a simple yet performant network device model that can be easily supported in different operating systems and hypervisors. We prove the effectiveness of our approach by comparing ptnet's performance with one of the state of the art I/O virtualization solutions, namely VirtIO on Linux and QEMU/KVM. ptnet is available under a BSD license as part of the netmap distributions on github. Vincenzo Maffione, Luigi Rizzo, Giuseppe Lettieri |
LANMAN | 2 |
| 2016 | Very high speed link emulation with TLEMabstractIn this work we discuss the limitations of link emulators based on conventional network stacks, and present our alternative architecture called TLEM, which is designed to address current high speed links and be open to future speed improvements. TLEM is structured as a pipeline of stages, implemented with separate threads and with limited interactions with each other, so that high performance can be achieved. Our emulator can handle bidirectional traffic at speeds of over 18 Mpps (64 byte packets) and 40 Gbit/s (1500 byte packets) per direction even with large emulation delays. Even higher performance can be achieved with shorter delays, as the workload fits better into the L3 cache of the system. TLEM is distributed as BSD-licensed opensource as part of the netmap distributions, and runs on any system that supports netmap (this includes FreeBSD, Linux and now even Windows). Luigi Rizzo, Giuseppe Lettieri, Vincenzo Maffione |
LANMAN | 1 |
| 2015 | Virtual Device Passthrough for High Speed VM NetworkingabstractSupporting network I/O at high packet rates in virtual machines is fundamental for the deployment of Cloud data centers and Network Function Virtualization. Historically, SR-IOV and hardware passthrough were thought as the only viable solution to reduce the high cost of virtualization. In previous work [15] we showed how even plain device emulation can achieve VM-to-VM speeds of millions of packets per second (Mpps), though still at least 3 times slower than bare metal. In this paper, to fill this gap, we present ptnetmap, a virtual passthrough network device (based on the netmap framework). ptnetmap allows VMs to connect to any netmap port (physical devices, software switches, netmap pipes), conserving the speed and isolation of the native netmap system, and removing the constraints of hardware passthrough. Our work includes two key features not present in previous proposals: we provide a high speed path also to untrusted VMs, and do not require dedicated polling cores/threads, which is fundamental to achieve an efficient use of resources. Besides these features, our speed is also beyond previously published values. Running on top of ptnetmap, VMs can saturate a 10 Gbit link at 14.88 Mpps, talk at over 20 Mpps to untrusted VMs, and over 70 Mpps to trusted VMs. ptnetmap extends the netmap framework, and currently supports Linux and FreeBSD guests, and QEMU/KVM host. Support for bhyve/FreeBSD host is under development. Stefano Garzarella, Giuseppe Lettieri, Luigi Rizzo |
ANCS | 3 |
| 2015 | Rollback-Recovery for MiddleboxesabstractNetwork middleboxes must offer high availability, with automatic failover when a device fails. Achieving high availability is challenging because failover must correctly restore lost state (e.g., activity logs, port mappings) but must do so quickly (e.g., in less than typical transport timeout values to minimize disruption to applications) and with little overhead to failure-free operation (e.g., additional per-packet latencies of 10-100s of us). No existing middlebox design provides failover that is correct, fast to recover, and imposes little increased latency on failure-free operations. We present a new design for fault-tolerance in middleboxes that achieves these three goals. Our system, FTMB (for Fault-Tolerant MiddleBox), adopts the classical approach of "rollback recovery" in which a system uses information logged during normal operation to correctly reconstruct state after a failure. However, traditional rollback recovery cannot maintain high throughput given the frequent output rate of middleboxes. Hence, we design a novel solution to record middlebox state which relies on two mechanisms: (1) 'ordered logging', which provides lightweight logging of the information needed after recovery, and (2) a `parallel release' algorithm which, when coupled with ordered logging, ensures that recovery is always correct. We implement ordered logging and parallel release in Click and show that for our test applications our design adds only 30$\mu$s of latency to median per packet latencies. Our system introduces moderate throughput overheads (5-30%) and can reconstruct lost state in 40-275ms for practical systems. Justine Sherry, Peter Xiang Gao, Soumya Basu 0003, Aurojit Panda, Arvind Krishnamurthy, Christian Maciocco, Maziar Manesh, Sylvia Ratnasamy, Luigi Rizzo, Scott Shenker |
SIGCOMM | 10 |
| 2015 | E2: a framework for NFV applicationsabstractBy moving network appliance functionality from proprietary hardware to software, Network Function Virtualization promises to bring the advantages of cloud computing to network packet processing. However, the evolution of cloud computing (particularly for data analytics) has greatly benefited from application-independent methods for scaling and placement that achieve high efficiency while relieving programmers of these burdens. NFV has no such general management solutions. In this paper, we present a scalable and application-agnostic scheduling framework for packet processing, and compare its performance to current approaches. Shoumik Palkar, Chang Lan, Sangjin Han, Keon Jang, Aurojit Panda, Sylvia Ratnasamy, Luigi Rizzo, Scott Shenker |
SOSP | 7 |
| 2015 | On service guarantees of fair-queueing schedulers in real systems
Luigi Rizzo, Paolo Valente |
Comput. Commun. | 1 |
| 2013 | Speeding up packet I/O in virtual machinesabstractMost of the work on VM network performance has focused so far on bulk TCP traffic, which covers classical applications of virtualization. Completely new “paravirtualized devices” (Xenfront, VIRTIO, vmxnet) have been designed and implemented to improve network throughput. We expect virtualization to become widely used also for different workloads: packet switching devices and middleboxes, Software Defined Networks, etc.. These applications involve very high packet rates that are problematic not only for the hypervisor (which emulates network interfaces) but also for the host itself (which switches packets between guests and physical NICs). In this paper we provide three main results. First, we demonstrate how rates of millions of packets per second can be achieved even within VMs, with limited but targeted modifications on device drivers, hypervisors and the host's virtual switch. Secondly, we show that emulation of conventional NICs (e.g., Intel e1000) is perfectly capable of achieving such packet rates, without requiring completely different device models. Finally, we provide sets of modifications suitable for different use cases (acting only on the guest, or only on the host, or on both) which can improve the network throughput of a VM by 20 times or more. These results are important because they enable a new set of applications within virtual machines. In particular, we achieve guest-to-guest UDP speeds of over 1 Mpps with short frames (and 6 Gbit/s with 1500-byte frames) using a conventional e1000 device, and socket-based sender/receivers. This matches the speed of the OS on bare metal. Furthermore, we reach over 5 Mpps when guests use the netmap API. Our work requires only small changes to device drivers (about 100 lines, both for FreeBSD and Linux version of e1000), similarly small modifications to the hypervisor (we have a QEMU prototype available) and the use of the VALE switch as a network backend. Relevant changes are being incorporated and/or distributed as external patches for FreeBSD, QEMU and Linux. Luigi Rizzo, Giuseppe Lettieri, Vincenzo Maffione |
ANCS | 1 |
| 2013 | QFQ: Efficient Packet Scheduling With Tight GuaranteesabstractPacket scheduling, together with classification, is one of the most expensive processing steps in systems providing tight bandwidth and delay guarantees at high packet rates. Schedulers with near-optimal service guarantees andO(1) time complexity have been proposed in the past, using techniques such as timestamp rounding and flow grouping to keep their execution time small. However, even the two best proposals in this family have a per-packet cost component that is linear either in the number of groups or in the length of the packet being transmitted. Furthermore, no studies are available on the actual execution time of these algorithms. In this paper we make two contributions. First, we present Quick Fair Queueing (QFQ), a newO( 1) scheduler that provides near-optimal guarantees and is the first to achieve that goal with a truly constant cost also with respect to the number of groups and the packet length. The QFQ algorithm has no loops and uses very simple instructions and data structures that contribute to its speed of operation. Second, we have developed production-quality implementations of QFQ and of its closest competitors, which we use to present a detailed comparative performance analysis of the various algorithms. Experiments show that QFQ fulfills our expectations, outperforming the other algorithms in the same class. In absolute terms, even on a low-end workstation, QFQ takes about 110 ns for an enqueue()/dequeue() pair (only twice the time of DRR, but with much better service guarantees). Fabio Checconi, Luigi Rizzo, Paolo Valente |
IEEE/ACM Trans. Netw. | 2 |
| 2012 | VALE, a switched ethernet for virtual machinesabstractThe growing popularity of virtual machines is pushing the demand for high performance communication between them. Past solutions have seen the use of hardware assistance, in the form of "PCI passthrough" (dedicating parts of physical NICs to each virtual machine) and even bouncing traffic through physical switches to handle data forwarding and replication. Luigi Rizzo, Giuseppe Lettieri |
CoNEXT | 1 |
| 2012 | Transparent acceleration of software packet forwarding using netmapabstractSoftware packet forwarding has been used for a long time in general purpose operating systems. While interesting for prototyping or on slow links, it is not considered a viable solution at very high packet rates, where various sources of overhead (particularly, the packet I/O mechanisms) get in the way of achieving good performance. Having recently developed a novel framework (called netmap) for packet I/O on general purpose operating systems, we have investigated how our work can improve the performance of software packet processing. The problem is of interest because software switches/routers are widely used, and they are becoming inadequate with the increasing use of 1..10 Gbit/s links. The two case studies (OpenvSwitch and Click userspace) that we report in this paper give very interesting answers and insights. First of all, accelerating the I/O layer has the potential for huge benefits: we improved the performance of OpenvSwitch from 780 Kpps to almost 3 Mpps, and that of Click userspace from 490 Kpps to 3.95 Mpps, by simply replacing the I/O library (libpcap) with our accelerated version. On the other hand, reaching these speedups was not purely mechanical. The original versions of the two systems had other limitations, partly hidden by the slow packet I/O library, which prevented or limited the exploitation of these speed gains. In the paper we make the following contributions: i) present an accelerated version of libpcap which gives significant speedups for many existing packet processing applications; ii) show how we modified two representative applications (in particular, Click userspace), achieving huge performance improvements; iii) prove that existing software packet processing systems can be made adequate for high speed links, provided we are careful in removing other bottlenecks not related to packet I/O1. Luigi Rizzo, Marta Carbone, Gaetano Catalli |
INFOCOM | 1 |
| 2012 | Building a Power-Proportional Software Router
Luca Niccolini, Gianluca Iannaccone, Sylvia Ratnasamy, Jaideep Chandrashekar, Luigi Rizzo |
USENIX ATC | 5 |
| 2012 | netmap: A Novel Framework for Fast Packet I/O
Luigi Rizzo |
USENIX ATC | 1 |
| 2011 | netmap: memory mapped access to network devicesabstractRecent papers have shown that wire-speed packet processing is feasible in software even at 10~Gbit/s, but the result has been achieved taking direct control of the network controllers to cut down OS and device driver overheads. Luigi Rizzo, Matteo Landi |
SIGCOMM | 1 |
| 2011 | An emulation tool for PlanetLab
Marta Carbone, Luigi Rizzo |
Comput. Commun. | 2 |
| 2005 | Packet classification via improved space decomposition techniquesabstractPacket classification is a common task in modern Internet routers. The goal is to classify packets into "classes" or "flows" according to some ruleset that looks at multiple fields of each packet. Differentiated actions can then be applied to the traffic depending on the result of the classification. Even though rulesets can be expressed in a relatively compact way by using high level languages, the resulting decision trees can partition the search space (the set of possible attribute values) in a potentially very large (106 and more) number of regions. This calls for methods that scale to such large problem sizes, though the only scalable proposal in the literature so far is the one based on a fat inverted segment tree (A. Feldmann and S. Muthukrishnan). In this paper we propose a new geometric technique called G-filter for packet classification on d dimensions. G-filter is based on an improved space decomposition technique. In addition to a theoretical analysis showing that classification in G-filter has O(1) time complexity and slightly super-linear space in the number of rules, we provide thorough experiments showing that the constants involved are extremely small on a wide range of problem sizes, and that G-filter improve the best results in the literature for large problem sizes, and is competitive for small sizes as well. Filippo Geraci, Marco Pellegrini 0001, Paolo Pisati, Luigi Rizzo |
INFOCOM | 4 |
| 2002 | Guest editorial - network support for multicast communicationsabstract1441-1443 Don Towsley, Christophe Diot, Brian Neil Levine, Luigi Rizzo |
IEEE J. Sel. Areas Commun. | 4 |
| 2001 | Breaking the Lab's Walls: Tele-Laboratories at the University of PisaabstractIn this paper we describe work being done at our Department to make the Robotics laboratory accessible to students and colleagues, to execute and watch real-time experiments at any time and from anywhere. We describe few different installations, and highlight the underlying philosophy, which is aimed at enlarging the lab in all the dimensions of space, time, and available resources, through the use of Internet technologies. Antonio Bicchi, Alessandro Coppelli, Francesco Quarto, Luigi Rizzo, Aldo Balestrino |
ICRA | 4 |
| 2000 | pgmcc: a TCP-friendly single-rate multicastabstractWe present a single rate multicast congestion control scheme (pgmcc) which is TCP-friendly and achieves scalability, stability and fast response to variations in network conditions. pgmcc is suitable for both non-reliable and reliable data transfers; it uses a window-based TCP-like controller based on positive ACKs and run between the sender and a group's representative, the acker. The innovative part of pgmcc is a fast and low-overhead procedure to select (and track changes of) the acker, which permits us to consider the acker as a moving receiver rather than a changing one. As such, the scheme is robust to measurement errors, and supports fast response to changes in the receiver set and/or network conditions. The scheme has been implemented in the PGM protocol, and the paper presents a number of experimental results on its performance. Luigi Rizzo |
SIGCOMM | 1 |
| 2000 | Replacement policies for a proxy cacheabstractIn this paper, we analyze access traces to a Web proxy, looking at statistical parameters to be used in the design of a replacement policy for documents held in the cache. In the first part of this paper, we present a number of properties of the lifetime and statistics of access to documents, derived from two large trace sets coming from very different proxies and spanning over time intervals of up to five months. In the second part, we propose a novel replacement policy, called LRV, which selects for replacement the document with the lowest relative value among those in cache. In LRV, the value of a document is computed adaptively based on information readily available to the proxy server. The algorithm has no hardwired constants, and the computations associated with the replacement policy require only a small constant time. We show how LRV outperforms least recently used (LRU) and other policies and can significantly improve the performance of the cache, especially for a small one. Luigi Rizzo, Lorenzo Vicisano |
IEEE/ACM Trans. Netw. | 1 |
| 1998 | TCP-Like Congestion Control for Layered Multicast Data TransferabstractWe present a novel congestion control algorithm suitable for use with cumulative, layered data streams in the MBone. Our algorithm behaves similarly to TCP congestion control algorithms, and shares bandwidth fairly with other instances of the protocol and with TCP flows. It is entirely receiver driven and requires no per-receiver status at the sender, in order to scale to large numbers of receivers. It relies on standard functionalities of multicast routers, and is suitable for continuous stream and reliable bulk data transfer. In the paper we illustrate the algorithm, characterize its response to losses both analytically and by simulations, and analyse its behaviour using simulations and experiments in real networks. We also show how error recovery can be dealt with independently from congestion control by using FEC techniques, so as to provide reliable bulk data transfer. Lorenzo Vicisano, Luigi Rizzo, Jon Crowcroft |
INFOCOM | 2 |
| 1998 | Dummynet and Forward Error Correction
Luigi Rizzo |
USENIX ATC | 1 |
| 1997 | A hybrid approach to adaptive load sharing and its performance
Marco Avvenuti, Luigi Rizzo, Lorenzo Vicisano |
J. Syst. Archit. | 2 |
| 1996 | Hardware support for load sharing in parallel systems
Marco Avvenuti, Luigi Rizzo, Lorenzo Vicisano |
J. Syst. Archit. | 2 |