This paper proposes a new method for directly measuring alias-free aperture jitter in an ADC output. Both the average ENOB and the worst-case ENOB due to aperture jitter are also measured after the elimination of the aliasing noise. Because it adds only a negligible computation time to an existing ENOB test of a single frequency, it can also be used in an HV production environment and should reduce the overall test time by at least three times.

Is it possible to create analog fault models that are theoretically valid, experimentally verifiable, and computationally efficient to support test developments and quality improvements? This presentation challenges the audience to face this question heads-on, given the variety of analog fault models in use in the past twenty years. We will review various efforts, from those relying on mapping manufacturing defects to devices and circuits to others relying on process variations, block-level parametric variations, and circuit-level specification variations. While the impediments to the development of a standard analog fault model are obvious, the procedures to create such a model have never been elucidated, always left as future work to be done later. Well, the future is now. The presentation, with audience participation, seeks to outline possible procedures to solve this problem defined in the past yet still continuing to affect current and future technologies.

Evaluating the phase noise of a data stream may be accomplished with the Fast Fourier Transform (FFT) of the signal, if the resolution is high enough, or captured using a mixer and local oscillator. To eliminate these requirements, we present a method for capturing phase noise amplitude from arbitrary bit stream data using a Time to Digital Converter.

Recent analog designers do think about measurement at design time. Analog design-for-measurement is a real success, not based on test research but based on designers' incorporation of calibration methods to ensure that their circuits work within specifications. In the meantime, mixed-signal test research has not kept pace with new design architectures, and some analog designers have outpaced mixed-signal test/design-for-test researchers. This session will elucidate the key factors for this success and the differences between design and test. And the session will discusses a designers' and test researchers' roles on analog design-for-test from each viewpoint, and some challenges on collaborating designers and test researchers.

To reduce the test costs of phase noise measurements, we use all-digital methods to detect sinusoidal phase noise components while reducing the need for computation intensive FFT.

Recently, proposals have been made for enhancing the Oscillation Based Test (OBT) methodology by using non-plain oscillation regimes, leading to so called Complex Oscillation Based Test (COBT). Here we focus on a recently illustrated strategy for the testing of analog 2ndorder filters, showing that the COBT dynamics is quite similar to that expressed by Resonate & Fire (R+F) neuron models. In this interpretation, the testing approach can be related to firing-rate measures. A brief description is given of the mathematical models necessary to achieve a precise characterization of firing times, showing how it can be used for testing purposes. A practical example with simulation data is also provided.

This paper presents an improved design for a Level-Crossing ADC (LCADC) that incorporates both an equivalent- time method and a clocked comparator. The LCADC is experimentally validated using a 65 nm clocked comparator.

This paper introduces a new Level-Crossing ADC (LCADC) architecture which employs the novel use of a clocked comparator. The proposed LCADC can measure a timing noise spectrum with wide dynamic range and wide frequency range. An extension of the underlying theory of the performance measurement of an LCADC is also included.

Costs and difficulties associated to testing can be an Achilles' heel for modern large-scale mixed-mode systems. Here, a low-overhead technique is introduced to enable the design of analog filters capable of checking their own parameters. The approach can also be applied to add such functionality to existing filter designs. The case of a switched-capacitor 2ndorder band-pass stage is used for illustration. The approach is based on the recently introduced complex oscillation based test methodology and permits to appreciate not just deviations in characteristic frequencies, but also the merit factor (and thus bandwidth and roll-off).

Time domain measurement of a real oscillator output reveals non-ideal variation, commonly called jitter. This paper presents a new measurement method to test for the presence of a phase noise spur in an oscillator’s output. Models for some specific classes of jitter characterize noise in the time domain, namely: random jitter (RJ); and a sub-class of deterministic jitter (DJ), sinusoidal jitter (SJ). These models and analysis of m-cycle-to-m-cycle jitter enable estimation of phase noise power spectral density characteristics for an oscillators output. Specifically, m-cycle-to-m-cycle jitter extracted from time domain measurements characterize SNR for discrete spurious phase noise. Thus, this method uses time domain measurements to estimate the effect of real noise sources, such as digital switching noise that couples to the oscillator output, and appears as phase noise spurs in the frequency domain.

Four industry panelists will address the key issues in enhancing industry participation in ISCAS and the IEEE Circuits and Systems Society (CASS), with emphasis on industry benefits and possible changes in the Society operations. Significant time will be available for audience questions and participation.

This paper proposes a new method for measuring aperture jitter on an ADC output. It measures both the average ENOB loss and the worst-case ENOB loss due to aperture jitter. Because it adds only a negligible computation time to an existing ENOB test, it can also be used in an HV production environment without significantly increasing the overall test time.

We present a generic method for determining transfer function of a DUT using simple time-domain computations in place of conventional computationally intensive frequency domain methods. Our method uses a chirp stimulus and an average of absolute value to extract energy in different frequency bins. For an No-size spectrum, this enables a reduction of computational complexity from NoIn Nomultiply-accumulates (using an FFT) to Noaccumulates. This makes it an attractive strategy for BIST. We present the theoretical basis, test case simulations, and a comparison with the FFT method.

This paper proposes a new method for measuring clock jitter using a delta-time-to-voltage converter. The method has been implemented in 0.11-μm CMOS technology, and has been verified experimentally to at least 2.8 GHz.

This paper demonstrates a new low cost method for data jitter measurement. It shows that jitter in data steam can be accurately measured in real time by combining an interpolated data sequence with a delta-time-to-voltage converter. Experimental results using a 2.5-Gbps PRBS with injected sinusoidal jitter and DDJ are presented to illustrate the usefulness and accuracy of this method.

This paper proposes an FFT-based method that separates random jitter from deterministic jitter in clock and data patterns, with a 10X reduction in test time. The method has been verified experimentally on a 2.5 Gbps clock pattern & 7-stage PRBS, and gives results that are comparable to existing methods.

This paper introduces a new method for measuring clock jitter using a delta-time-to-voltage converter. The method employs a combination of loadboard circuitry and instrumentation, and has been verified experimentally to at least 2.488 GHz

This paper proposes a new cost-effective solution for jitter testing. It measures timing jitter using a combination of voltage comparators in the pin electronics as a 1.6-bit ADC, and digital signal processing. It has been verified experimentally to be more than 96% accurate

This work addresses the concurrent on-chip measurement of the gain, the input 1-dB compression point (ICP1-dB), and the input-referred third-order interference point (IIP3) of individual RF building blocks in RF front-end systems, using introduced high speed CMOS RF on-chip amplitude detectors, which work up to 20 GHz with high accuracy, small area, and low power consumption

This paper describes a statistical study of the effectiveness of state-of-the-art built-in-self-test (BIST) jitter measurement techniques. Many BIST solutions under-sample the signal under test, estimating the jitter in a system based upon a subset of the total number of clock edges. In this paper, we explore how under-sampling affects the accuracy of jitter measurements, and demonstrate a technique for estimating the actual jitter using a Gaussian distribution estimation. Our theoretical results were verified through a simulation study and comparison to experimental data collected from a 400 MHz phase-locked loop supplied by an industry sponsor.

The interaction between design and test is a matter of great importance in high-speed RF product development. In this paper, the guaranteed-by-design concept was evaluated. The quest for "guaranteed by design" increasingly runs into obstacles for various reasons.

This paper introduces a new method for measuring jitter in GHz signals using ATE. The wideband DeltaPhi method employs a frequency-shifting approach and has been verified experimentally to at least 2.5 GHz

A BIST method to measure jitter without external references is presented. Measured data from 0.25- m BiCMOS chips show jitter resolution about 30 to 50 ps over 8 cycles of a 1 GHz input signal. The measurement technique uses the clock signal under test to control the charging of the input capacitance of an ADC. One advantage of this design is that it does not require an external jitter-free reference clock or a voltage reference. Design improvements from architectures to circuits are discussed and the method has potentials in other timing measurement applications.

This work presents the design and performance results of a real-time jitter measurement board for testing high-frequency clocks and data transceivers. The board targets high-volume manufacturing test to measure sinusoidal jitter tolerance and random jitter in computer and communication systems, with a substantial reduction in test cost compared to existing equipment. The board meets jitter tolerance and random jitter measurement needs and is suitable for production testing.

This paper proposes a method and an on-chip test circuit to measure the center frequency and the bandwidth of RF front-end circuits using the peak amplitudes and the periods of the output signal in response to a realistic step input signal. The method is also suitable for implementation in external test instrumentation.

This paper presents the application of a new analytic signal method for measuring several different kinds of clock skew in the clock distribution network of microprocessors. First, key terms are defined, and other existing skew measurement methods are reviewed. Then, detailed steps are given for applying the new method for measuring skew between a master and distributed clocks, between two distributed clocks, and between different frequency clocks that are related by frequency division. An indirect procedure for measuring deterministic clock skew is also proposed. Next, the new method is validated with experimental data from a prototype microprocessor test. Performance comparison is performed between the analytic signal method and the two-probe method. Finally, the measurement requirements of the proposed analytic signal method are compared with those of conventional methods.

A BIST method measures accumulated jitter over N periods and requires no external references. Simulation using a 0.25um process shows a 625MHz - I GHz input range with resolution of 70ps RMS jitter occupying 0.05 75mmz area.

This paper presents a new jitter tolerance model that includes the effect of deterministic jitter in interconnects. First, it is shown by experiment that the deterministic jitter in a cable can significantly affect its jitter tolerance. Then, the new jitter tolerance model is verified with experimental data on cables of various lengths, using both PRBS and T11 test patterns. 1.

A method to measure time-varying phase and frequency of radio-frequency signals using the Morlet transform is presented. The theoretical analysis and simulation results show that the method is suitable for detecting phase jitter, phase discontinuities, and frequency contents in telecommunication signals.

In this paper, we investigate the problem of assigning scan cells to multiple scan chains based on physical placement. We formulate a new multichain assignment (MA) problem and discuss its complexity and relationship to partitioning and traveling salesman problems. We show that MA is not adequately solved by approaches based on the traveling salesman methods alone and present two new algorithms for MA based on partitioning and stable marriage (SM) problems. We demonstrate that even though partitioning-based methods offer significant improvements compared to previous methods, the SM-based algorithm offers the best results. We compare our algorithms with previous work based on preplacement and greedy assignments in terms of total scan net lengths and maximum load capacitance of scan cells. Experiments with ISCAS89 benchmarks indicate that our algorithms improve the chain lengths 50%-90%, while reducing the maximum load capacitance by 30%-50%.

This paper presents an experimental study of random jitter modulation in a commercial serializer-deserializer device to demonstrate the effects of possible amplitude modulation in jitter tolerance measurements. The paper recommends alternative methods for injecting random jitter to avoid this source of measurement error.

A wavelet-based timing parameter extraction method applicable to computer and communication systems is presented. Experimental validation of this theoretical method is demonstrated with clock jitter estimation on a prototype microprocessor, based on the PowerPC architecture, together with a comparison with existing techniques.

This paper presents a new method for measuring jitter tolerance of a SerDes receiver using the timing misalignment between the jittered source clock and the recovered clock. A sinusoidal jitter is injected into the serial bit stream. The method derives an equation for estimating BER accurately and is 10/spl times/ faster than the conventional BER test method The accuracy and test speed of the method are verified by 2.5 Gbps and 10 Gbps-SerDes experiments.

This paper presents a new method for measuring timing jitter of the bit clock signal in telecommunication devices operating at 10 Gbps. The method uses a divide-by-M circuit to reduce the frequency and the number of clock samples, and applies the Hilbert transform to measure the timing jitter The theory for this frequency division method is supported by the experimental data from a serializer-deserializer device.

Experimental results are presented for the defect-oriented testing of PLLs using the charge-based frequency measurement BIST technique. Using National Semiconductor Corp.'s 0.25 /spl mu/m CMOS 900 MHz PLL, we demonstrate a low-cost and practical BIST solution. The area overhead is minimized by using the existing PLL circuitry for the BIST structure. The test time is typically 12 /spl mu/sec, significantly faster than conventional testing.

This paper presents an application of a new analytic signal method for measuring clock skews in the clock distribution network of microprocessors. The method can measure skews between the master system clock and distributed clocks, between two distributed clocks, or between clocks whose frequencies are related by frequency division. Experimental data using a PowerPC/sup TM/ microprocessor is presented for validation.

This paper introduces the extended /spl Delta//spl phi/ method for measuring cycle-to-cycle period jitter in PLL outputs. The theoretical basis for this method is derived from the limited condition for the average period and analytic signal theory. Sinusoidal jitter measurements verify the relationship between cycle-to-cycle period jitter and timing jitter. To validate the method, experimental data from jitter measurements on a PowerPC/sup TM/ microprocessor is analyzed in the frequency domain. Comparisons of phase quantization errors are made between the extended /spl Delta//spl phi/ method and the conventional zero-crossing method.

This paper demonstrates a new method for measuring both peak-to-peak and RMS jitter in PLL output signals. The theoretical basis for this method is derived from analytic signal theory. To validate the method, experimental data from PowerPC/sup TM/ microprocessor jitter measurements is compared with results obtained with the conventional time interval analyzer (TIA) technique.

We propose a new method of defect-oriented testing of PLL using charge-based frequency measurement BIST (CF-BIST) technique. As no test stimulus is required and the test output is pure digital, low-cost and practical implementation of on-chip BIST for a PLL is possible. Fault simulations using the 900 MHz PLL from National Semiconductor Corp. show higher fault coverage than previous test methods.

This paper proposes a new method based on analytic signal theory for extracting both instantaneous and RMS sinusoidal jitter from PLL output signals. The method relies on the extension of a real signal into an analytic signal by utilizing the Hilbert transform. Both the theoretical basis and fundamental concepts of the proposed method are explained. A review of conventional testing methods is also presented. Results of Matlab simulations validate the performance of the proposed method for measuring random jitter. The method is further validated by comparing experimental sinusoidal jitter results with those measured with a time interval analyzer.

A quick literature survey revealed that many researchers have and continue to work on automatic test pattern generation for analog and mixed-signal circuits and systems, however, very few if any have addressed the problem of test set size. This paper presents a novel test set compaction algorithm which takes a generated test set and maximally reduces the number of test vectors required while maximizing the fault coverage. Results show that 58.33% reduction can be achieved. Smaller test set implies lower total test time and long test times have been identified as one of the bottlenecks in analog and mixed-signal test.

This paper presents a digital scheme to correct undesired skews between couples of clocks of synchronous systems. Correction is automatically and very fastly performed during system run-time. The proposed scheme is self-checking with respect to a wide set of possible internal (permanent as well as temporary) faults, and is easily scalable to account for different skew tolerance/sensitivity requirements. It is suitable to be implemented in VLSI, very deep submicron technology, as well as using field programmable gate arrays.

The question raised by the panel is how much testing should be included in a VLSI Design course and what makes a “well-rounded” electrical and computer engineering graduate. The fact that we had to have a National Science Foundation workshop and now an ITC panel to discuss how to incorporate test in a design course shows that the disconnect between design and test happens not only in industry but also in academia as well. The fact that the panel considers test in conjunction with VLSI design seems to imply that test is important only in the VLSI design context. How did we get to this sorry state? Can we do better and look at test as an integral part of electronic design, instead of narrowing the focus to just VLSI? At the University of Washington, we have shown that by taking a more global perspective, we can actually teach test, teach it very well, attract interested and well-motivated students, and build a new generation of students knowledgeable in both design and test.

This paper presents an algorithm based on testability measurement for test point insertion of mixed-signal circuits. Two transfer function models compatible with analog models are proposed: one is for digital devices and the other is for A/D interface components. An industry power supply circuit and a common A/D converter circuit are used to validate our approaches.

In this paper, we present methods for constructing optimal tests to detect structural faults in analog integrated circuits in the presence of process variation. The analog test determination problem is formulated as selecting an optimal subset from an initial large set of tests with optimality criteria defined in terms of fault coverage and fault separation on a given fault set. The process variation may be represented either deterministically by box constraints or statistically as random variables. Each of these representations require different methods for computing the detectabilities. In the deterministic case, the detectability measures are computed by a combination of analytical and numerical optimization techniques. Such an approach helps reduce the number of simulations by up to three times over traditional Monte Carlo methods. This approach produces more compact test sets compared to a linear sensitivity analysis while being closer in accuracy to the Monte Carlo method. In the statistical case, the detectability measures are computed as separation distances between the good and faulty distributions. These distributions represented nonparametrically are generated by traditional Monte Carlo techniques. Once the deterministic or statistical detectabilities are computed for the entire test set, a test compaction step is performed which is a covering problem. On solving this covering problem eve get a test set with optimal fault coverage and fault separation.

In this paper, we present an approach to construct a set of dynamic test signals for analog circuits and systems. Testability transfer factors are introduced and we use them as the basis to construct an efficient test set. Fault detectability and fault coverage are defined. Two circuits from the suite of analog and mixed-signal circuits are used to evaluate our approach. The fault coverage is 100% for both circuits studied. The approach presented may be used to construct inputs signals for the selection of an external stimulus applied through an arbitrary waveform generator.

Fast and efficient test generation techniques are key to reducing the current high cost of testing analog circuits. A new multi-frequency test generation technique for detecting catastrophic failures in this class of circuits is presented. Testability transfer factors are introduced and we use them to construct an efficient test set for analog circuits. Fault detectability and fault coverage are also defined. Two circuits from the suite [4] of analog and mixed-signal benchmark circuits are used to validate our approach.

This paper presents the design of current-mode circuits for analog scan, which include the highly accurate current-mirror scan latches and the analog shift registers. Experimental data from a test chip fabricated in Orbit 2-micron CMOS Foresight process illustrates that the accuracy of the circuits is sufficient for use in analog on-chip scan-based testing. The interface between analog scan and the P1149.4 test bus is discussed to show system-level applications of this technique.

The IEEE Mixed-Signal Technical Activity Committee is developing a common set of benchmark circuits for use in researching and evaluating analog fault modeling, test generation, design-for-test, and built-in self-test methodologies. The first release circuits are based on MITEL Semiconductor's 1.5 /spl mu/m and 1.2 /spl mu/m CMOS technologies and they will allow engineers and researchers working in analog and mixed-signal testing to compare test results as is done in the digital domain. This paper presents a set of typical circuits described by netlists in HSPICE format. Schematic diagrams, simulation results and measured results, if available, are provided together with layout and a typical test environment. The full details are available on the web page dedicated to analog and mixed-signal benchmarks.

This paper introduces a new method for evaluating non-idealities in ADCs using wavelet transforms. Compared with conventional testing methods, this method can shorten the test time and improve test quality during production testing of ADCs.

This paper describes a new procedure to estimate the delay-dependent switching activities in CMOS combinational circuits. The procedure is based on analytic and statistical approaches to take advantage of their time-efficiency over conventional event-driven simulation tools. For this study, combinational circuits driven by discrete-time logic signals are considered. By focusing on a specific class of combinational circuits, the transitional effects can be analyzed more accurately by considering some of the delay effects neglected in previous studies, Also, to model the delay-dependent effects, statistical properties such as the pattern probability, the propagation probability, and the distribution of the propagation delay of switching activities are defined and evaluated. The simulation results on benchmark circuits indicate that the proposed procedure significantly speeds up the estimation process in comparison to the conventional event-driven simulators. The reliability issues in the aspect of switching activities are briefly discussed.

Article Free Access Share on A statistical approach to the estimation of delay-dependent switching activities in CMOS combinational circuits Authors: Yong Je Lim University of Washington, Department of Electrical Engineering, BOX 352500, Seattle, WA University of Washington, Department of Electrical Engineering, BOX 352500, Seattle, WAView Profile , Kyung-Im Son University of Washington, Department of Electrical Engineering, BOX 352500, Seattle, WA University of Washington, Department of Electrical Engineering, BOX 352500, Seattle, WAView Profile , Heung-Joon Park University of Washington, Department of Electrical Engineering, BOX 352500, Seattle, WA University of Washington, Department of Electrical Engineering, BOX 352500, Seattle, WAView Profile , Mani Soma University of Washington, Department of Electrical Engineering, BOX 352500, Seattle, WA University of Washington, Department of Electrical Engineering, BOX 352500, Seattle, WAView Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996 Pages 445–450https://doi.org/10.1145/240518.240603Published:01 June 1996Publication History 5citation202DownloadsMetricsTotal Citations5Total Downloads202Last 12 Months2Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

In this work we present a behavioral fault simulation technique for mixed-signal ICs, wherein a robust function approximation method namely regression splines are applied to automatically extract behavioral block parameters. The use of these robust high-level functions enables true behavioral fault simulation while preserving the statistical dependence on the process tolerance. We demonstrate significant speed-up over traditional Monte Carlo methods for two typical mixed-signal circuits, a sigma-delta modulator and a PLL.

In this paper we present an approach to construct dynamic test signals for analog circuits. Using the integral measure for characterizing time-domain signals, we extend the minmax formulation of the static test problem to the dynamic case. A sub-optimal solution strategy, similar to dynamic programming methods is used to construct the test waveforms. The approach presented here may be used to construct input signals for an on-chip test scheme or for the selection of an external stimulus applied through an arbitrary waveform generator.

The paper describes a design-for-test technique for switched-capacitor (SC) filters to improve controllability and observability of internal nodes. Timing strategies employing existing clock phases in SC circuits are used to sensitize signal propagating paths, thus enhancing the circuit testability. The overhead in terms of extra control logic is small (several simple gates). Since there are no extraneous devices inserted in the analog signal path, there is no performance penalty in the normal operation of the filters.>

This paper describes a technique which uses the differential non linearity (DNL) test data for fault location and identification of the analog components of a flash ADC. In a flash ADC, a fault in the analog subcircuit is uniquely reflected in the transfer function and therefore also in DNL data. This property is exploited to locate a fault and to identify the error value in analog components of the flash ADC. The technique proposed here relies only on DNL test data. Thus the diagnosis can be carried out using at-operating-speed test data. The paper presents relationship between each fault case and its respective DNL pattern. Fault simulation results of a small flash ADC are presented.>

The test quality of DC parametric manufacturing test sets is evaluated versus the open fault model for analog amplifiers. Using two case studies in CMOS and bipolar technologies, the fault coverage of the test set is shown to be rather low (less than 80%). Several open faults in the signal path remain undetected. When the amplifiers are embedded in a larger circuit, the functional test set is usually unable to detect these faults as well. Detection is strongly correlated to circuit topology in two signal processing circuits used as examples. Test selection guidelines are presented

A study of fault equivalence in mixed analogue-digital circuits and systems is presented, emphasizing both the theoretical analysis of the equivalence concept as well as experimental results from three classes of circuits: sample-and-hold, digital-to-analog converter, and analog-to-digital converter. While fault equivalence is well understood in digital fault models, the concept is still quite new for analog fault models. The concept is also valid within the context of mixed-signal fault models, but the equivalence has to be defined in the frequency domain and in some cases, has to be approached from a probabilistic perspective. The experimental results include fault effects due to the classic digital stuck-at-fault models as well as analog faults such as out-of-specification performance, nonlinearity, etc. For each class of circuit, extensive simulation is conducted to study the fault behavior and experimental measurements are carried out to verify these behaviors as well as to confirm the validity of equivalence definition. The major application of this study is in test generation and fault diagnosis, similar to the application of digital equivalent faults in defining test vectors for equivalence classes.>

The minimal modification of the basic cell of various iterative logic arrays to make them C-testable is investigated. The overhead is measured in terms of the number of additional columns and rows to be added in the flow table of the basic cell. One-dimensional unidirectional arrays without vertical outputs, one-dimensional bidirectional arrays with vertical outputs, and two-dimensional unidirectional arrays are considered. The overhead of the present approach is shown to be smaller than that of previous approaches. It is demonstrated that two extra columns and two extra rows are enough to make any arbitrary two-dimensional orthogonal unidirectional array C-testable.>

The authors have implemented three concurrent fault simulation algorithms and applied them to several circuit families. The algorithms are concurrent fault simulation (CFS), hierarchical concurrent fault simulation (HCFS), and a modification of HCFS called bundled hierarchical fault simulation (BHCFS). In BHCFS, a structure is imposed upon the simulation error lists, which can produce a significant reduction in simulation run time. A prototype of each algorithm has been applied to circuit families of varying size to generate actual run-time data. The circuits are scalable (to some granularity) in gate count. This property allows the simulator run-time data to be presented as a function of circuit size without the effects of varying circuit topology. It is shown experimentally that the run time for BHCFS grows nearly linearly with acyclic circuit gate count but approaches a higher order in tightly connected sequential circuits. It is also confirmed that HCFS exhibits near N log N behaviour in circuits which have reasonably well-balanced design hierarchy. In absolute run time, both hierarchical algorithms outperformed flat CFS at the gate level in all examples except one, which had an extremely unbalanced hierarchy. Overall, BHCFS shows the best performance in acyclic circuits and good performance in loosely coupled sequential circuits.>

A DFT (design-for-test) methodology to improve the controllability/observability of internal signals in active filters is presented. The normal filter design becomes an 'analog scan' structure in the test mode. The fundamental theory underlying the proposed methodology is presented, followed by an algorithmic description and the results of several case studies. These results are considered from the perspectives of the overhead incurred and the extension of the technique to other analog structures. The DFT algorithm includes not only the modification technique but also a test generation scheme. The algorithm is suitable for silicon compiler and CAD (computer-aided-design) implementation. Experimental results confirm the validity of the methodology.>

This paper presents the design of a mixed digital/analog array to implement several signal processing algorithms used in coordinate rotation for image processing. The advantages of hybrid arrays in which the processor element can be either analog or digital depending on a specific computing requirement are discussed. The interfaces between processor elements of different types are considered and several circuits are designed for this task. The proposed mixed array architecture is shown to possess strong potential in other high-performance computing applications.

A simple probabilistic model of a two-layer neural net is proposed to quantize the fault tolerance characteristics of the network from circuit design perspectives. While the model assumes very simple distribution functions and an elementary architecture, the results illuminate the design tradeoffs that must be considered, especially in VLSI implementations. The methods to quantize fault tolerance that are presented are applicable to more complicated probability distributions and architectures.>

A BIST (built-in self-test)-compatible method for the design, layout, and test of structured logic arrays is presented. The layout is analyzed for realistic faults in the conducting layers of a typical CMOS process. It is found that only one-third of the faults while occurring as a result of random spot defects are classical stuck faults while others have to be manipulated by the appropriate test vectors to manifest themselves as stuck faults further down in the circuit. Many of these faults are detected by the test method adopted without any special provisions in the circuit. This technique eliminates the need for placing shift registers and exclusive-OR gates on the product lines of the array.>

A method of bundling error data is proposed which should significantly reduce the amount of explicit functional evaluation required for hierarchical concurrent simulation. The bundling operation is carried out at run time, and so is different from but complementary to approaches such as WRAP, which compress unnecessary or uninteresting portions of circuit hierarchy. The technique is exact; it does not cause the simulation to become probabilistic. This work extends the concept of multilist traversal (MLT). A hierarchy is imposed on the conventional machine list which matches the design hierarchy of the circuit under simulation. The resulting improvement in machine-list organization is expected to prevent multiple evaluations of behavioral primitives for collections of faults which present the same input value.>