Data augmentation is an effective method to improve model robustness and generalization. Conventional data augmentation pipelines are commonly used as preprocessing modules for neural networks with predefined heuristics and restricted differentiability. Some recent works indicated that the differentiable data augmentation (DDA) could effectively contribute to the training of neural networks and the augmentation policy searching strategies. Some recent works indicated that the differentiable data augmentation (DDA) could effectively contribute to the training of neural networks and the searching of augmentation policy strategies. This survey provides a comprehensive and structured overview of the advances in DDA. Specifically, we focus on fundamental elements including differentiable operations, operation relaxations, and gradient estimations, then categorize existing DDA works accordingly, and investigate the utilization of DDA in selected of practical applications, specifically neural augmentation networks and differentiable augmentation search. Finally, we discuss current challenges of DDA and future research directions.

An unmanned aerial vehicle (UAV) integrated with the remote sensing technology of light detection and ranging (LiDAR) can provide accurate and real-time road traffic information. In this paper, we propose to equip UAVs with LiDAR sensors for Intelligent Transportation Systems (ITS) applications. The goal is to find the optimal 3D placement of multiple UAV-LiDAR (ULiDs) for a given road segmentation. We formulate an optimization problem to find the optimal placement such that the road coverage efficiency is maximized. The optimization problem is constrained by notable ULiD specifications such as field-of-view (FoV), point-cloud density, geographic information system (GIS) location, and road segment coverage priorities. We propose to use a computational intelligent algorithm based on particle swarm optimization to solve the problem. Finally, we illustrate the benefits of using our proposed algorithm over other baselines.

Standard NNs should not be employed mindlessly in critical applications due to their incapability to express the uncertainty of their predictions. On the other hand, Bayesian Neural Networks (BNNs) can measure the uncertainty of their predictions. There are two methods for BNN inference, the Monte Carlo-based method, which requires the sampling of weights distributions and multiple inference iterations, and moment propagation, where the mean and variance of a normal distribution are propagated through the BNN. Hardware implementations of moment propagation BNN inference consume less power than Monte Carlo because they complete the inference in a single forward pass. However, because the propagation of distribution moments through nonlinear activation functions leads to large hardware designs, these functions are usually approximated by polynomials. Hardware implementations of moment propagation have been studied solely for fully-connected neural networks while lacking optimal accuracy due to the approximation of the ReLU activation function with a single polynomial term. Therefore, in this work, we add one more polynomial term in the approximation of ReLU, providing better accuracy with negligible additional hardware. We also propose a polynomial approximation for another common activation function, tanh, and extend the hardware implementation to Convolutional Neural Networks (CNNs). Experimental results demonstrated that the proposed approximation of ReLU outperforms the previously suggested single-term polynomial by achieving up to 5.9% higher accuracy with merely up to 0.029$W$power overhead.

The proliferation of Light Detection and Ranging (LiDAR) technology in the automotive industry has quickly promoted its use in many emerging areas in smart cities and internet-of-things. Compared to other sensors, like cameras and radars, LiDAR provides up to 64 scanning channels, vertical and horizontal field of view, high precision, high detection range, and great performance under poor weather conditions. In this paper, we propose a novel aerial traffic monitoring solution based on Light Detection and Ranging (LiDAR) technology. By equipping unmanned aerial vehicles (UAVs) with a LiDAR sensor, we generate 3D point cloud data that can be used for object detection and tracking. Due to the unavailability of LiDAR data from the sky, we propose to use a 3D simulator. Then, we implement PointVoxel-RCNN (PV-RCNN) to perform road user detection (e.g., vehicles and pedestrians). Subsequently, we implement an Unscented Kalman filter, which takes a 3D detected object as input and uses its information to predict the state of the 3D box before the next LiDAR scan gets loaded. Finally, we update the measurement by using the new observation of the point cloud and correct the previous prediction's belief. The simulation results illustrate the performance gain (around 8 %) achieved by our solution compared to other 3D point cloud solutions.

The globalization of the Integrated Circuits (ICs) supply chain has increased threats from untrusted entities involved in the process. Various threats, such as the insertion of hardware Trojans, counterfeiting, cloning, overproduction, etc., have emerged as a potential challenge in the ICs supply chain. Several mechanisms are widely used to ensure hardware security, like logic locking, watermarking, split manufacturing, etc. In this work, we propose a different approach to designing a Finite State Machine (FSM) inspired hardware-based watermarks using the unique physical characteristic of spin-orbit torque-based Magnetic Tunnel Junction (MTJ). Watermarks are helpful to authenticate proof of ownership and are a widely acclaimed strategy against the counterfeiting of chips. We discuss the design strategy involved in detail, the strategy to use the VLSI CAD tool to harness the unique ability of MTJ, such as non-volatility and dependence on an external magnetic field for guiding the information through a specific sequence of states in an FSM. Furthermore, the performance prospects are analyzed using Monte-Carlo simulations, and security aspects are described to ensure a more robust and practical application.

The wide usage of the Clustered Regularly Inter-spaced Short Palindromic Repeats associated with the Cas9 enzyme (CRISPR/Cas9) system, which is one of the latest genome-editing methods, has shed light on pathways that were inconceivable before, from enhancing fruit nutrition to treating incurable diseases. The precise prediction of single guide RNA (sgRNA) on-target knockout efficacy poses a substantial challenge to the practical application of CRISPR/Cas9 systems. Although many Machine Learning (ML)-based techniques have yielded encouraging results, prediction accuracy still needs improvement. CRISPR/Cas9 datasets do not contain many examples for training the models. Generative Adversarial Networks (GAN)s are good at learning a model for generating new training data given a dataset. This work proposes a novel Machine Learning model that combines Convolutional Neural Networks and conditional GANs (coGAN)s to predict sgRNA on-target knockout efficacy. Experimental results showed that the proposed model could outperform other models proposed in the literature in regression and classification tasks for predicting the on-target sgRNA cleavage efficacy in CRISPR/Cas9 systems.

Microwave Imaging (MWI) has emerged as a potential candidate for brain stroke detection due to its low cost, time efficiency and accurate nature when compared to other screening techniques. TinyML is a revolutionary technique for utilizing AI in portable and low-powered devices. The need for more compact and concise systems grows by the day in order to provide smart services, particularly in the medical arena. This paper tries to fulfil these requirements by presenting the first-ever portable MWI-based TinyML brain stroke detection system with high accuracy. The head-imaging dataset, utilized here for the training of models, provides open-source data generated by our prototype head imaging system consisting of a low-cost vector network analyzer, single-board computer, rotating motor setup, and a Vivaldi antenna. The Tiny ML model is a compressed-size model of our proposed Deep Learning (DL) framework that obtains an accuracy of 93% on testing data with an F1-score of 0.929 deployed on the single-board computer. The compressed model obtained by pruning or quantization is not only small in size but also retains the above 90% accuracy of the DL model. This work reassures the possibility of successful deployment of Tiny ML- based solutions in microwave imaging systems for medical diagnostic applications in low-resource settings.

Breast Microwave Imaging (BMI) has emerged as a competitive and potentially disruptive alternative to conventional breast cancer screening techniques owing to its desirable features and improved detection rate. In this paper, we apply various artificial intelligence, and deep learning approaches for automatic breast tumor detection, classification and localization in an open-source experimental BreastCare dataset obtained using our pre-clinical, portable and cost-effective BMI system. We compare the effectiveness of various cutting-edge machine-learning detection algorithms to assess the usefulness of the obtained data-set. Also, we present a deep learning framework that outperforms state-of-the-art microwave imaging methods and ML algorithms for tumor detection, localization, and characterization. The proposed framework gives promising results using our BMI system's measured reflection coefficients ($S_{11}$). This work shows the potential advantages of applying cutting-edge deep learning algorithms in practical BMI systems.

The experience of using project-based learning (PBL) methods is talked about in the context of training STEM (science, technology, engineering, and math) students for the real-world scenarios in the industry. In this paper, a PBL strategy is proposed as a pedagogical tool targeting undergraduate engineering and CS+[X] students through the design of a biomedical imaging system for breast cancer detection. The primary goals of this interdisciplinary project are, firstly, to train students to implement the theoretical knowledge towards design of engineering product directly targeting one or more sustainable development goals; secondly, to motivate students to choose to learn more about biomedical imaging system development while appreciating the need of interdisciplinary approach in solving a complex engineering problem; and finally, to make students realize the need for technological innovations in the development of portable and cost-effective diagnostic products for developing countries. During the design and implementation of this project, students' competencies have improved significantly which reassures the usefulness of PBL as a pedagogical approach in student-centered learning.

We present the living lab methodology as a pedagogical approach to artificial intelligence (AI) based autonomous systems under the framework of place-based learning. Due to time, location, weather, traffic safety, and other issues, performing road testing on autonomous cars is challenging. Autonomous driving testing has been made easier by the virtual test platform, which can partly replace road testing. To improve the system-designed skills of the students and to validate autonomous driving ideas in real life settings to further refine solutions proposed, we proposed Mini-Living Lab system. The platform may also give a significant number of test scenarios for the driver during early verification of the autonomous driving control approach. We provide the detailed system design and implement an artificial intelligence based autonomous driving model on our proposed system. For the neural network model, we adopt PointNet++ and improve its design to process the lidar point cloud data, then further to perform the autonomous steering control tasks. The proposed project provides an opportunity for students to actively participate in co-creation of knowledge and innovation in real-life contexts, thus leading to an enhanced understanding of complex engineering problems and development of required skills for their innovative solutions.

Owing to ample potential and versatile capabilities of artificial intelligence to solve intricate scientific problems, two regression-based artificial neural network (ANN) models are proposed to design and optimize nano-structured meta-atoms. The proposed forward predicting ANN depicts that considering the complete structural and material information of the cylindrical nano-pillar meta-atoms could predict the corresponding electromagnetic (EM) response (amplitude and phase of transmission) with a mean squared error (MSE) as low as$\mathbf{2.1}\times \mathbf{10}^{-\mathbf{3}}$. Thus, it replaces the conventional EM simulations performed using high-end commercial software's, while significantly saving time and computational resources. Inverse design deep-learning model is also presented, which is connected with the pre-trained forward model and trained in a tandem architecture to provide an optimum set of dimensions and material, given the target response as its input. Furthermore, a comparative study regarding the number of hidden layers of the ANN and the amount of training dataset size is performed for the proposed forward and tandem inverse models to analyze the effect of considering extra underlying physics related information, i.e., wavelength regime and the EM spectral information. This study reveals that considering the extra information can lead to a significant reduction in the obtained MSE. Specifically, the proposed model could achieve a decent MSE even with a smaller amount of training dataset. Hence, the use of artificial intelligence models significantly reduces the training time and computational complexity of the proposed solution.

This study proposes a new algorithm for parameter estimation of the electric circuit model of Lithium (Li)-ion battery. The first-order battery-electric circuit model is considered in this work that resembles battery charging and discharging behaviors. The battery circuit element values have been modeled as polynomial equations with unknown coefficients. An accurate estimation of the battery circuit element values is profound to accurately find the battery State of Charge (SoC), an immeasurable quantity required in battery management systems (BMS). The ElectroStatic discharge algorithm (ESDA) is used in this study to estimate the unknown polynomial coefficients and, in turn, the values of the battery circuit elements. The accuracy of the proposed ESDA in estimating the battery circuit element values is compared to the recently proposed Artificial Hummingbird Optimization Technique (AHOT), Chameleon Swarm Algorithm (CSA), and Tuna Swarm Optimization (TSO). The results demonstrate the superiority of the proposed algorithm for charging and discharging in battery parameters estimation over the other algorithms with an accuracy gain of at least 10%.

Photovoltaic (PV) arrays, when subjected to Partial Shading (PS), exhibit several power losses due to diminished current across the array. Therefore, bypass diodes are connected across array modules to avoid the PS effect. Although they reduce the PS effect, the bypass diodes make the Power versus Voltage (P- V) relation of a PV non-convex. This paper investigates the Maximum Power Point Tracking (MPPT) problem under PS conditions to track the PV array's Maximum Power Point (MPP). Because previously proposed algorithms for this problem either failed to track the MPP or were computationally expensive, we propose a modified version of the Bat metaheuristic algorithm with dynamically narrowing search space (DNSS) exploration to avoid exploring low-power regions. The results show around 35 % gain in terms of rapidity and efficiency of the proposed metaheuristic approach in mitigating power losses compared to other existing algorithms.

Photovoltaic (PV) forecasting plays a major role in residential and industrial PV installation as well as penetration with the grid. An inaccurate PV power forecasting may result in increased monetary and energy losses. This study proposes a metaheuristic-based strategy for accurate PV power forecasting using a heuristic-based data-driven PV model. The proposed algorithm integrates a dense explorative strategy with the existing PV equation knowledge by a multilayer perceptron (MLP) network with Sigmoid activation functions to predict the best coefficients for the inputs of the data-driven PV model. The proposed method is compared to a recently proposed metaheuristic algorithm, the artificial hummingbird optimizer algorithm (AHOA). The comparison is performed for inside distribution (ID) and out-of-distribution (OOD) irradiance datasets and with varying temperatures. The results prove that the proposed NN-based algorithm achieves higher accuracy in PV power parameter prediction and hence forecasting.

Future communication systems are expected to employ Reconfigurable intelligent surfaces (RIS) for real-time manipulation of channel to achieve unprecedented efficiency and quality of service (QoS) improvement. Here, we have designed a practical RIS-enabled communication setup to demonstrate beam steering and multi-beam forming in near-to far-field trials. The design of RIS as a component of wireless communication system has many variables that dictate path loss compensation capability of RIS. We investigate RIS path loss compensation by varying RIS size with point source and plane wave source using a 1-bit RIS of size$27\times 28$unit-cells. It is observed that RIS size has less significance compared to phase quantization, in the near field while the effect of RIS size is dominant in the far field. The reported results provide useful insights for design of RIS-enabled wireless communication systems.

The accurate decoding of ElectroEncephaloGraphy (EEG) signals would bring us closer to understanding brain functionality, opening new pathways to fixing brain impairments and devising new Brain-Computer Interface (BCI)-related applications. The impressive success of deep convolutional neural networks extracting information from raw data in computer vision and natural language processing has motivated their investigation into EEG signal decoding. Consequently, a number of deep convolutional neural network models with state-of-the-art performance have been proposed in the literature for EEG signal decoding. However, because all these works aimed to find the model architecture with the best decoding accuracy, the model's size was left unbounded in that exploration. Considering the model size in the design of deep convolutional neural networks for EEG decoding could make their implementation on low-power microcontrollers (that may be integrated into a wearable system) with limited memory feasible. Thus, in this paper, we search for the most accurate deep convolutional neural network on the BCI Competition IV 2a dataset that can also fit in a microcontroller with less than 256KB SRAM. Specifically, we use a Neural Architecture Search (NAS) algorithm that considers, apart from the model's accuracy, the model size, the latency, and the peak memory utilization when running the model's inference. We compare our models with the model with the best decoding accuracy in the literature on the BCI Competition IV 2a dataset (baseline). We show that the discovered models could achieve similar accuracy to the baseline model while shrinking the memory footprint during inference by a factor of ≈ ×20, with a speedup in latency of up to ×1.7 on average.

A better understanding of ElectroEncephaloGraphy (EEG) and ElectroCorticoGram (ECoG) signals would get us closer to comprehending brain functionality, creating new avenues for treating brain abnormalities and developing novel Brain-Computer Interface (BCI)-related applications. Deep Convolutional Neural Networks (deep CNNs) have lately been employed with remarkable success to decode EEG/ECoG signals. However, the optimal architectural/training parameter values in these deep CNN architectures have received little attention. In addition, new data-driven optimization methodologies that leverage significant advancements in Machine Learning, such as the Transformer model, have recently been proposed. Because an exhaustive search on all possible architectural/training parameter values of the state-of-the-art deep CNN model (our baseline model) decoding the motor imagery EEG and finger tension ECoG signals comprising the BCI IV 2a and 4 datasets, respectively, would require prohibitively much time, this paper proposes a model-based optimization technique based on the Transformer model for the discovery of the optimal architectural/training parameter values for that model. Our findings indicate that we could pick better values for the architectural/training parameters of the baseline model, enhancing the accuracy of the baseline model by 3.4% in the BCI IV 2a dataset and by 29.8% in the BCI IV 4 dataset.

In this paper, we investigate an innovative car-following framework where a self-driving vehicle, identified as the follower, autonomously follows another leading vehicle. We propose to design the car-following strategy based only on the environmental LiDAR data captured by the follower and the GNSS input. The proposed framework is composed of several modules, including the detection module using the PointNet++ neural network, the continuous calculation of the leader's driving trajectory, and the trajectory following control module using the BP-PID method. Comparison experiments and analysis have been performed on the Carla simulator. Results show that our proposed framework can work effectively and efficiently in the defined car-following tasks, and its success rate exceeds that of the Yolo-v5-based method by more than 13% under night conditions or rainy weather settings.

With process technology scaling, accurate gate-level timing analysis becomes even more challenging. Highly resistive on-chip interconnects have an ever-increasing impact on timing, signals no longer resemble smooth saturated ramps, while gate-interconnect interdependencies are stronger. Moreover, efficiency is a serious concern since repeatedly invoking a signoff tool during incremental optimization of modern VLSI circuits has become a major bottleneck. In this paper, we introduce a novel machine learning approach for timing estimation of gate-level stages using current source models and the concept of multiple slew and effective capacitance values. First, we exploit a fast iterative algorithm for initial stage timing estimation and feature extraction, and then we employ four artificial neural networks to correlate the initial delay and slew estimates for both the driver and interconnect with golden SPICE results. Contrary to prior works, our method uses fewer and more accurate features to represent the stage, leading to more efficient models. Experimental evaluation on driver-interconnect stages implemented in 7 nm FinFET technology indicates that our method leads to 0.99% (0.90 ps) and 2.54% (2.59 ps) mean error against SPICE for stage delay and slew, respectively. Furthermore, it has a small memory footprint (1.27 MB) and performs 35× faster than a commercial signoff tool. Thus, it may be integrated into timing-driven optimization steps to provide signoff accuracy and expedite timing closure.

Driver behavior profiling is one of the main issues in the insurance industries and fleet management, thus being able to classify the driver behavior with low-cost mobile applications remains in the spotlight of autonomous driving. However, using mobile sensors may face the challenge of security, privacy, and trust issues. To overcome those challenges, we propose to collect data sensors using Carla Simulator available in smartphones (Accelerometer, Gyroscope, GPS) in order to classify the driver behavior using speed, acceleration, direction, the 3-axis rotation angles (Yaw, Pitch, Roll) taking into account the speed limit of the current road and weather conditions to better identify the risky behavior. Secondly, after fusing inter-axial data from multiple sensors into a single file, we explore different machine learning algorithms for time series classification to evaluate which algorithm results in the highest performance.

Electricity generation using photovoltaic (PV) technology has become highly popular recently. However, natural barriers such as trees, buildings, bird drops, etc., cause partial shading (PS) on the PV surface resulting in high power losses. Bypass diodes used to mitigate the PS effect cause multiple peaks in the PV power delivery. The tracking of the optimal power peak can be considered an optimization problem with a continuously changing objective function due to different insolation conditions. All optimization strategies applied in previous works spanning from mathematical programming techniques to Machine Learning and the recently proposed Nature-inspired algorithms led to either sub-optimal maximum power or required extensive computations. This work presents an algorithm that combines the advantages of the previous works and avoids their loopholes. Experimental results indicate the superiority of the proposed algorithm over the state-of-the-art algorithm for the Maximum Power Peak Tracking problem.

Collaborative mobile crowdsourcing (CMCS) allows entities, e.g., local authorities or individuals, to hire a team of workers from the crowd of connected people, to execute complex tasks. In this article, we investigate two different CMCS recruitment strategies allowing task requesters to form teams of socially connected and skilled workers: 1) a platform-based strategy where the platform exploits its own knowledge about the workers to form a team and 2) a leader-based strategy where the platform designates a group leader that recruits its own suitable team given its own knowledge about its social network (SN) neighbors. We first formulate the recruitment as an integer linear program (ILP) that optimally forms teams according to four fuzzy-logic-based criteria: 1) level of expertise; 2) social relationship strength; 3) recruitment cost; and 4) recruiter’s confidence level. To cope with NP-hardness, we design a novel low-complexity CMCS recruitment approach relying on graph neural networks (GNNs), specifically graph embedding and clustering techniques, to shrink the workers’ search space and afterwards, exploiting a metaheuristic genetic algorithm to select appropriate workers. Simulation results applied on a real-world data set illustrate the performance of both proposed CMCS recruitment approaches. It is shown that our proposed low-complexity GNN-based recruitment algorithm achieves close performances to those of the baseline ILP with significant computational time saving and ability to operate on large-scale mobile crowdsourcing platforms. It is also shown that compared to the leader-based strategy, the platform-based strategy recruits a more skilled team but with lower SN relationships and higher cost.

Successful portfolio management requires, in addition to advanced optimization strategies, effective recruitment of specialized financial advisors. Hiring the wrong ones can be detrimental to investors' financial goals. In this article, we propose an automated crowdsourcing system to organize cooperation between financial advisors and investors. Without interfering with their private portfolio optimization techniques, we design a recruitment framework that matches financial advisors to investors based on their profiles and features, as well as the previous activities of their peers. Using the database of the crowdsourcing platform, we employ an unsupervised technique to regroup advisors with a high degree of similarities into clusters and, hence, shrink the search space. Afterward, we train a machine learning regression model to predict the matching score that can be achieved if an investor hires a particular advisor. These scores are converted to weights of bipartite graphs to which we apply a double-phased many-to-many maximum weight matching algorithm to determine a suitable investor-advisor combination. In the simulations, we investigate the performance of the proposed recruitment approach and show that, compared with other traditional approaches, higher returns can be reached for both investors and financial advisors.

In this paper, we propose an autonomous UAV path planning framework using deep reinforcement learning approach. The objective is to employ a self-trained UAV as a flying mobile unit to reach spatially distributed moving or static targets in a given three dimensional urban area. In this approach, a Deep Deterministic Policy Gradient (DDPG) with continuous action space is designed to train the UAV to navigate through or over the obstacles to reach its assigned target. A customized reward function is developed to minimize the distance separating the UAV and its destination while penalizing collisions. Numerical simulations investigate the behavior of the UAV in learning the environment and autonomously determining trajectories for different selected scenarios.

Biometric observation using portable and wearable sensors is transforming health monitoring since patients can now have their conditions frequently checked outside the hospital setting. However, modern biosensors mostly use the standard printed circuit board substrate, which is physically incompatible with irregular-surface applications. The need for a flexible, low-cost and high-resolution monitoring device for observing elderly patient mobility out of hospital settings is the motivation driving this research. The following paper is a characterization of an experimental inkjet-printed sensor that circumvents the problem of rigidity by using a highly flexible substrate while also benefiting from low fabrication costs, low power usage, and environmental friendliness. The sensor is a 4 × 4 grid of Aluminum-doped Zinc Oxide nodes inkjet-printed on paper-based substrates. The tests performed show nodes are capable of responding to applied pressures of over 540 PSI. Notably, they exhibit sensitivity to heat and humidity without shielding measures, making it more useful for physical therapy. Power usage of the device is shown to be as low as 5 μW. Silver nanoparticle ink was chosen as electrical routing between the Zinc Oxide and data collection scheme. The analog signal is connected through ELVIS II+ analog pins, where a MATLAB script retrieves and stores the data for visual analysis. The cost of printing a single pressure node of this sensor is estimated to be $0.01. These conditions make it a monetarily attractive pressure sensing and mapping option for human impact monitoring applications.

In this paper, we propose to design an automated service discovery process to allow mobile crowdsourcing task requesters select a small set of devices out of a large-scale Internet-of-things (IoT) network to execute their tasks. To this end, we proceed by dividing the large-scale IoT network into several virtual communities whose members share strong social IoT relations. Two community detection algorithms, namely Louvain and order statistics local method (OSLOM) algorithms, are investigated and applied to a real-world IoT dataset to form non-overlapping and overlapping IoT devices groups. Afterwards, a natural language process (NLP)-based approach is executed to handle crowdsourcing textual requests and accordingly find the list of IoT devices capable of effectively accomplishing the tasks. This is performed by matching the NLP outputs, e.g., type of application, location, required trustworthiness level, with the different detected communities. The proposed approach effectively helps in automating and reducing the service discovery procedure and recruitment process for mobile crowdsourcing applications.

Recently, elevated LiDAR (ELiD) has been proposed as an alternative to local LiDAR sensors in autonomous vehicles (AV) because of the ability to reduce costs and computational requirements of AVs, reduce the number of overlapping sensors mapping an area, and to allow for a multiplicity of LiDAR sensing applications with the same shared LiDAR map data. Since ELiDs have been removed from the vehicle, their data must be processed externally in the cloud or on the edge, necessitating an optimized backhaul system that allocates data efficiently to compute servers. In this paper, we address this need for an optimized backhaul system by formulating a mixed-integer programming problem that minimizes the average latency of the uplink and downlink hop-by-hop transmission plus computation time for each ELiD while considering different bandwidth allocation schemes. We show that our model is capable of allocating resources for differing topologies, and we perform a sensitivity analysis that demonstrates the robustness of our problem formulation under different circumstances.

The widespread use of advanced mobile devices has led to the emergence of a new class of mobile crowdsourcing called spatial mobile crowdsourcing (SMCS). The main feature of SMCS is the presence of spatial tasks that require workers to be physically present at a particular location for task fulfillment. These tasks usually take advantage of the built-in sensors in mobile devices by requesting environment sensing services. Because cameras are becoming the most common way for visual logging techniques and sensing in our daily lives, we propose, in this article, a photo-based SMCS framework for event reporting. The proposed framework allows event report requesters to solicit photos of ongoing events and keep track of any updates. We propose a full architecture in which we solve the SMCS recruitment problem using different fairness strategies in the presence of multiple events and reporters. Then, once submissions are received and before forwarding final responses to event requesters, we proceed with a data processing phase for data quality monitoring. In short, our event reporting platform helps requesters recruit ideal reporters, select highly relevant data from an evolving picture stream, and receive accurate responses. This solution mainly incorporates: 1) a strategic and generic recruitment algorithm for recruiting and scheduling suitable reporters to events; 2) a deep learning model that eliminates false submissions and ensures photo's credibility; and 3) an A-tree shape data structure model for clustering streaming pictures to reduce information redundancy and provide maximum event coverage. Experiment results investigate the performances of the proposed recruitment approach and show that our algorithm outperforms two other benchmarking approaches. Also, we conduct simulations to evaluate the strategies of the proposed recruitment algorithm, given different fairness levels among events. Data quality simulation results show effectiveness in reducing false submissions and delivering high-quality responses. Finally, framework implementation for real-world applications is provided.

This contribution presents a solution to improve the performances of micro unmanned aerial vehicles (UAVs) by increasing their missions coverage in terms of distance and time. This is achieved by letting the UAV ride existing land public transport such as the city bus throughout the route to its mission location. Indeed, due to their limited battery capacity, micro-UAVs flying time is restrained, which affects their mission and coverage performances. In this paper, we propose to leverage the use of public transport infrastructure, such as city buses, to carry the UAVs whenever it is possible in order to minimize their flight energy consumption. For this purpose, a generic scheduling framework to efficiently cover spatially and temporally distributed events in a geographical area of interest over a long period of time is proposed. By considering the public transport schedule table, a mixed integer linear programming problem (MILP) aiming at minimizing the total energy consumption of the UAVs is formulated while accomplishing all the pre-scheduled missions. The proposed proactive UAV scheduling framework optimizes the UAV trips according to the mission occurrence and the schedule table of the buses. The obtained results demonstrate the effectiveness of the collaboration between the UAVs and the land transport to improve the overall UAV missions' performances in terms of distance coverage.

The use of micro unmanned aerial vehicles (UAVs) have gained a lot of interests especially for smart city applications due to their three- dimensional (3D) mobility and flexibility. Path planning is one of the most important UAV problems that needs to be addressed. In this paper, we focus on determining the optimal routes for a fleet of UAVs in urban cities that minimize the total arrival time of all UAV swarms while respecting their energy consumption constraints and avoiding the risk of collision. Through a mixed integer linear program, we develop a safe navigation framework for realistic 3D maps where charging stations are made available to recharge UAV batteries on their ways to destination. Our results investigate different scenarios for selected system parameters and illustrate different collision avoidance techniques followed by the UAVs.

Thermal-based flow monitoring has found widespread applications due to its noncontact measurement, high sensitivity, low flow resistance, miniaturization, ease of integration, and low-power consumption. In this work, a low-cost and affordable inkjet-printed graphene-based thermal sensor is integrated with a low-power CMOS circuit for flow rate monitoring. The custom inkjet-printed sensor consists of a silver nanoparticle interdigitated pattern with a coating of graphene, all printed on a glossy photo-paper substrate. The sensor read-out circuit is an energy-efficient current-starved ring oscillator. The sensor current controls the bias current of a current-starved ring oscillator and modulates the output frequency. A driver circuit then transforms the output to a square wave pulse signal. The scheme is designed and fabricated using the 0.13-μm standard CMOS process and occupies an area of 1.5 mm × 1.7 mm. Test results indicate that the prototype ring oscillator circuit consumes 19-90 μW for an oscillation frequency variation of 517 kHz-6.45 MHz. The output frequency variation with sensor current shows linear performance with R2= 0.9966.

In this paper we propose a design optimization technique for integrated DC-DC converters. We present a formulation of the relationships between the various converter parameters and numerical techniques for efficiently solving these formulations. These formulations capture the parasitic effects in the integrated converter and enable mitigating such effects. Mainly, we develop a relationship between the switching frequency and the inductor's inductance, which allows us to use a single-variable optimization technique to find the optimal design that would minimize the power losses in the converter. These relationships stem from the constraints on the system, which we use to achieve optimal and robust performance.

Integrated dc-dc converters are widely used for the realization of power converters suitable for energy harvesting and computing systems. In such systems, integrated converters are the ideal candidate due to their small size and low power consumption. Integrated dc-dc converters typically use spiral inductors to achieve high levels of integration and performance. However, under scenarios where energy scarcity is paramount, the integrated converter with spiral inductor requires careful modeling and optimization to achieve maximum efficiency. In this paper, we provide a parasitic aware design technique that takes into account the spiral inductor resistance as well as the switching parasitics, while utilizing numerical methods, to arrive at converter designs with robust performance and optimal efficiency. We translate the various system constraints into design rules and use them to formulate the various design parameters, from switching frequency to duty cycle, in terms of the inductance. We study how these parameters are dependent on each other, giving rise to multiple tradeoffs. We also present a method for minimizing power losses using optimization techniques, which leverage our formulation of the system parameters in terms of inductance.

Meeting the pressing power and bandwidth requirements of modern communication systems requires the development of highly efficient reconfigurable transceivers. On the receiver side, we present a new class of reconfigurable receiver that utilizes random projections to balance the power-bandwidth tradeoff. Such random projection front-ends are ubiquitous and allow the use of sub-Nyquist ADCs. These systems utilize high speed DACs, typically found in transmitters, to generate high fidelity random signals. The emergence of RF-DACs, used for direct digital-to-RF synthesis, can be leveraged for random projection reconfigurable receivers. However, the need for high output power and linearity in both the transmitter and receiver DACs forces an evaluation of RF-DAC topologies with respect to drain efficiency. In this paper, the power efficiencies of several RF-DAC topologies are compared.

Due to their orthogonality and nearly constant pulse widths, Modified Hermite Pulses (MHPs) have shown a great potential to enhance the data rate of UWB communications by creating M-ary or multiple access parallel systems. However, the potential high power dissipation required by the pulse set generation and the frequency shifting has limited their utilization in practice. In this paper, we propose a novel computation-efficient model for MHP set generators. Compared with existing models, the proposed model has made it feasible to design a power-efficient MHP set generator. Utilizing our proposed model along with neuromorphic circuit level implementations, we have developed an ultra-low power architecture for MHP set generation for sub-GHz (0 - 960 MHz) UWB communications. Results from both the mathematical analysis and the design layout simulations illustrate the effectiveness of the proposed scheme for the design of a power-efficient MHP set generator.

In this paper we derive conditions for bounding the state change in a memristor due to an applied signal. The main memristor functionality is a programmable resistor, but its resistance changes due to the signal passing through it. Therefore, it is necessary to guarantee that any signal through the memristor causes a small resistance change as tolerable by the application. The derived conditions relate the desired bound on the resistance change to a bound on the signal flux through the memristor. We show examples for the case of a sinusoidal signal and demonstrate the impact of the derived conditions on the design of memristor-based systems.

Random demodulation provides a hardware-compact architecture for realizing compressive sensing systems. A random demodulator is realized by a mixer, with a random signal as the oscillator, and a low pass filter. In order to recover the original signal from the compressive sensing measurements, accurate modeling of the hardware components is needed. Typically, the reconstruction model assumes the low pass filter to be an ideal integrator. While this assumption is valid at low frequencies, it poses tremendous challenges at frequencies higher than 50MHz. In this paper, we provide an accurate and efficient model for the random demodulator that takes into account the actual structure of the filter. Using our model at reconstruction allows random demodulation for bandwidths extending to the GHz range, while, as we demonstrate, assuming an ideal integrator at reconstruction severely limits the system bandwidth.

Spike detectors are important data-compression components for state-of-the-art implantable neural recording microsystems. This paper proposes two improved spike detection algorithms, frequency-enhanced nonlinear energy operator (fNEO) and energy-of-derivative (ED), to solve the sensitivity reduction of a conventional nonlinear energy operator (NEO) in the presence of baseline interference. The proposed methods are implemented in two analog spike detectors with a standard 0.13-μm CMOS process. To achieve an ultra-low-power design, weak-inversion MOSFET based multipliers, adders and derivative circuits are developed to work with a 0.5 V power supply. The power dissipations of the proposed fNEO spike detector and the ED spike detector are 258.7 nW and 129.4 nW, respectively. Quantitative investigations based on the standard deviation and peak-to-clutter ratio of the detected spikes indicate that the proposed spike detector schemes hold higher sensitivity than the conventional NEO based spike detector.

Memristors-based memories utilize the memristor's resistance programmability and small structure to realize high density non-volatile memories. This programmability arises from the dependence of the memristor's resistance on the magnetic flux and total charge, rather than the voltage and current passing through it. However, a critical requirement in memory applications is that the reading scheme should preserve the memristor state after the read. In this paper, we propose a robust reading scheme for memristor-based memories that uses a differential pair sensing amplifier.

Memristors promise to allow high levels of compaction in computing systems because these elements combine memory and switching functionality. This can be utilized to overcome some of the hardware challenges in compressive sensing architectures. In this paper, we propose a compressive sensing system architecture that uses a memristor-based random modulator. The gains of using such a memristor-based modulator mainly stem from replacing memory blocks and many of the switching components typically used in compressive sensing. We discuss some of these benefits and the design considerations that need to be addressed in memristor-based compressive sensing architectures.

This paper presents an ultra-low-power low-noise bioamplifier for neural recording applications. The bioamplifier manifests a supply insensitive first gain stage and a CMOS-inverter-based second gain stage. The entire system is designed in 0.13-µm standard RF CMOS process. The bioamplifier operates at 0.6 V supply with a power consumption of only 198.6 nW. The midband gain of the amplifier is 24.94 dB with a lower cut-off frequency at 0.1 Hz and a higher cut-off frequency at 9.51 KHz. The input-referred noise of the proposed bioamplifier is 0.9133 µVrms.

Upper extremity prosthetic limbs have succeeded in providing people affected by disabilities such as amputation or paralysis the ability to perform simple manual tasks. Typically, prosthetic limbs are controlled by electromyography (EMG) signals read from the muscles of the patient. As the capabilities of prosthetic hands improve toward those of the intact human hand, their mechanical complexity increases, making the development of advanced techniques for reading and interpreting these EMG signals, while pushing down the power consumption of the sensing device is becoming more critical. In this work, we investigate the classification EMG signals acquired using the technique of compressive sensing, which provides solutions for reducing sensor power and complexity by relaxing the constraints posed by the Shannon sampling theorem on the rate at which the analog signals, in general, should be sampled for preserving the signal's information. We show that using compressive sensing, we can reduce the sampling rate by at least 10 times while maintaining classification accuracy higher than 95%.

Biomedical implants have been developed in the recent years with a focus for continuous and real-time monitoring of physiological parameters. Battery-less operation of the implanted unit requires energy harvesting from an inductive link or from the neighboring environment. For efficient conversion of harvested energy to a usable DC level, a rectifier block is employed. However conventional CMOS full bridge rectifier incurs a significant amount of power loss and lowers the overall efficiency of the powering system. In this work a cross-coupled MOSFET based LC oscillator structure has been presented as a modified rectifier circuit. Cross-coupled structure minimizes the loss of the MOS switches and LC tank circuit boosts up the output DC level. The rectifier unit has been designed and simulated using 0.5-μm standard CMOS process. For simulation purposes, different biomedical frequency bands are used to validate the effectiveness of the proposed circuit. Simulation results show that the proposed rectifier circuit can achieve 75% PCE compared to the conventional full bridge CMOS rectifier of only 3% PCE.

In this paper, we investigate the crosstalk-induced delay, noise, and chemical mechanical polishing (CMP)-induced thickness-variation implications of dummy fill generated using rule-based wire track fill techniques and CMP-aware model-based methods for designs implemented in 65 nm process technology. The results indicate that fill generated using rule-based and CMP-aware model-based methods can have a significant impact on parasitic capacitance, interconnect planarization, and individual path delay variation. Crosstalk-induced delay and noise are significantly reduced in the grounded-fill cases, and designs with floating fill also experience a reduction in average crosstalk-induced delay and noise, which is in contrast to the predictions of previous studies on small-scale interconnect structures. When crosstalk effects are included in the analysis, the observed delay behavior is significantly different from the delay modeled without considering crosstalk effects. Consequently, crosstalk-induced delay and noise must be simultaneously considered in addition to parasitic capacitance and interconnect planarization when developing future fill generation methods.

In this paper, we develop a generalized automated design method-ology for tunable impedance matching networks in reconfigurable wireless systems. The method simultaneously determines the fixed and tunable/switchable circuit element values in an arbitrary-order canonical filter for a general set of performance constraints over a discrete or continuous set of operating frequencies and source/load impedances. To solve the filter design problem, we combine deter-ministic nonlinear constrained optimization using Sequential Quad-ratic Programming with a systematic constraint relaxation approach to facilitate convergence. Using the proposed methodology, we successfully generate three different reconfigurable impedance match-ing networks with performance requirements that would be difficult to realize using manual design techniques.

Given the fast growth of battery-powered wireless communication devices, developing customizable low-voltage low-noise amplifiers (LNAs) and mixers has become a crucial design consideration in RF front ends. In this paper, we present a low-voltage LNA-mixer pair design based on the common-gate topology. Current-reuse, current bleeding, and charge injection techniques are utilized in order to maximize the gain with minimal additive power consumption. Leveraging our analytical models, the design space can be explored to optimally design the LNA-mixer pair for customizable operating frequency. Simulation results demonstrate the performance improvement using our design technique.

As process technology continues to scale into the nanometer regime, the interplay between dummy fill metal placement and interconnect thickness variation due to chemical mechanical polishing (CMP) has become increasingly important for performance, reliability, and yield. This paper provides the first simultaneous investigation of both the interconnect capacitance increases and the CMP-induced thickness variations associated with rule-based and model-based fill generation methods. The results indicate that dummy fill can have a significant impact on both parasitic capacitance and interconnect planarization for large-scale designs implemented in 65 nm technology. We also demonstrate that model-based methods can simultaneously provide smaller incremental capacitance increases and better interconnect planarization compared to rule-based techniques.

In this paper, we develop a variability-aware design methodology for reconfigurable filters used in multi-standard wireless systems. To model the impact of statistical circuit component variations on the predicted manufacturing yield, we implement several different analytic variability quantification techniques based on a double-sided implementation of the first and second order reliability methods (FORM and SORM), which provide several orders of magnitude improvement in computational complexity over statistical sampling methods. Leveraging these efficient analytic variability quantification techniques, we employ an optimization approach using Sequential Quadratic Programming to simultaneously determine the fixed and tunable/switchable circuit element values in an arbitrary-order canonical filter to improve the overall robustness of the filter design when statistical variations are present. The results indicate that reconfigurable filters and impedance matching networks designed using the proposed methodology meet the specified performance requirements with a 26% average absolute yield improvement over circuits designed using deterministic techniques.

In this paper, we present a comprehensive model for the resistance in graphene nanoribbon (GNR) interconnects. We use the recent experimental and theoretical results to model the impact of stacking of graphene layers in multi-layer GNR interconnects. We compare the resistance of GNR interconnects with both single-walled carbon nanotube (SWCNT) bundle interconnects and conventional copper interconnects. Our simulation results demonstrate the performance superiority of multi-layer GNR interconnects over conventional copper interconnects at small widths (Lt 15 nm). Consequently, multi-layer GNR interconnects demonstrate a great potential to replace conventional copper interconnects in future technologies.

In this paper, we investigate the performance of a plasmonic nanostrip waveguide as a transmission line. We show that a nanostrip waveguide allows for subwavelength single-mode propagation. We present an analytical model of the characteristic impedance, which effectively captures the impacts of metal strip and dielectric film thicknesses as well as plasmonic effects. We show that the characteristic impedance model can be used as a reliable tool to design compact plasmonic components.

Given the spatial and temporal randomness of soft and permanent errors in the state-of-the-art system-on-chips (SoCs), dynamic routing algorithms that can adapt themselves accordingly are highly required for network-on-chip (NoC) applications. In this paper, we present a new dynamic routing algorithm for NoC applications that has the ability to locate and deal with both static and dynamic permanent failures and distinguish them from soft errors. In addition, our presented algorithm has the advantage of distributing the load over the whole network by considering the stress factors. Simulation results demonstrate the advantage of our routing algorithm in terms of functionality, latency, and energy consumption compared to directed flooding based fault tolerant routing algorithms in the presence of both soft errors and permanent faults. Our algorithm can achieves 1.95 times less latency and consumes 3.15 times less energy consumption on average.

In this paper, we present an adaptive circuit design that is capable of increasing the effective size-ratio of combinational logic gates to extend the balanced operation in the subthreshold region as well as to maintain high performance at the nominal Vdd. We optimize the sizes of the PMOS transistors in the pull-up network for minimum power dissipation and propagation delay over a wide range of supply voltage. In addition to the minimized energy operation, the dynamically adjustable gate size-ratio allows the gate to preserve a symmetric voltage transfer characteristic at both normal supply and subthreshold operation, which translates to maximized noise margins. Simulation results show that up to 70.9% reduction in the energy can be achieved for a ring oscillator, as compared to the fixed size design capable of operating under supply voltage in the range of 75 mV to 1.2 V Our adaptive circuit design presents an efficient solution for minimum energy circuit operation while preserving the high performance capability at the nominal VDD.

With state of the art technology scaling, the problem of delay variability due to power supply variations is becoming more and more critical. This paper addresses the problem of analyzing the speed degradation in synchronous systems caused by power supply IR-drop in deep submicron CMOS devices. Considering the impact of power supply variation on the clock skew value, violations of the timing constraints equations are presented. To satisfy the timing constraints over a range of 20% of VDDvariation, a 42% increase in the operational clock period has to be met with circuits operating at 2 GHz and implemented on 65 nm CMOS technology.

In this paper, we present an accurate method for analytical derivation of CMOS clock buffers delay under power supply variations. The method involves modeling of the pull-up and pull-down resistances using approximated drain saturation current device equations for the buffers together with lumped resistive capacitive elements for the interconnects. Compared to circuit simulation results, the analytical model provides more than four orders of magnitude speedup while maintaining an average error of 0.26% with 3.0% standard deviation over the entire range of power supply and circuit parameters variations, making it suitable for timing analysis and optimization.

As CMOS technology is pushed to its basic physical limits, alternate technologies are required for the realization of interconnect in future high performance integrated circuits. In this paper, we develop a generalized design technique for carbon nanotube (CNT) bundle-based interconnect, which we use to examine the performance limits and fabrication requirements for future nanotube-based interconnect solutions. The results indicate that optimized nanotube bundles can provide up to a 69% delay reduction in 22 nm process technology, and the optimal design method decreases delay by 21% and 29% on average compared to non-optimized multi-walled and single-walled CNT bundles. We also find that future CNT bundle fabrication processes must achieve a nanotube area coverage of at least 30% for optimized CNT bundles and 40% for non-optimized CNT bundles to obtain competitive performance results compared to copper interconnect.

The exponential growth of wireless portable device market has been increasing the demand for customizable power- efficient transceivers. In this paper, we present an efficient modeling methodology for common-gate low-noise amplifiers (LNAs). Leveraging our models, we designed LNAs to work for different communication standards, GSM at 900 MHz, Bluetooth at 2.4 GHz, and wireless-LAN at 5.6 GHz. Our methodology achieves about 96.45% average accuracy in predicting different figures of merit (FOM) at the center frequency, while it provides Ave orders of magnitude speedup in the design process compared to simulation-based modeling techniques.

In this paper, we successfully demonstrate the feasibility of hardware implementation of a sub-Nyquist random sampling based analog to information converter (RS-AIC). The RS-AIC is based on the theory of information recovery from random samples using an efficient information recovery algorithm to compute the spectrogram of the signal. Our RS-AIC enables sub-Nyquist acquisition and processing of wideband signals that are sparse in a local Fourier representation. Results from our RS-AIC hardware implementation demonstrate successful reconstruction of signals that are sampled at half the Nyquist-rate while maintaining up to a 51 dB signal-to-noise ratio (SNR), which is equivalent to an 8.5 bit resolution analog to digital converter.

As process technology continues to scale into the nanoscale regime, interconnect plays an ever increasing role in determining VLSI system performance. As the complexity of these systems increases, reduced order modeling becomes critical. In this paper, we develop a new method for the model order reduction of interconnect using frequency restrictive selection of interpolation points based on the spectral-zeros of the RLC interconnect model's transfer function. The methodology uses the imaginary part of spectral zeros for frequency selective projection and provides stable as well as passive reduced order models for interconnect in VLSI systems. For large order interconnect models with realistic RLC parameters, the results indicate that our method provides more accurate approximations than techniques based on balanced truncation and moment matching with excellent agreement with the original system's transfer function.

In the paper, we develop a systematic methodology for modeling sampled interconnect frequency response data based on spline interpolation. Through piecewise polynomial interpolation, we are able to avoid the numerical problems associated with global polynomial fitting and generate higher order systems to model simulated or measured wideband frequency response data. We reduce the complexity of the generated systems using a data point pruning algorithm and by applying model order reduction based on balanced truncation. The methodology provides substantially greater accuracy than global polynomial approximation while only having O(n) growth in model complexity.

Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper interconnect. In this paper, we evaluate the performance and reliability of nanotube bundles for future VLSI applications. We develop a scalable equivalent circuit model that captures the statistical distribution of metallic nanotubes while accurately incorporating recent experimental and theoretical results on inductance, contact resistance, and ohmic resistance. Leveraging the circuit model, we examine the performance and reliability of nanotube bundles including inductive effects. The results indicate that SWCNT interconnect bundles can provide significant improvement in delay over copper interconnect depending on the bundle geometry and process technology.

In this paper, we present a systematic synthesis methodology for fully integrated wideband low noise amplifiers that simultaneously optimizes impedance matching, noise figure, and other performance parameters. Leveraging an accurate analytical model, we hierarchically couple global optimization techniques with local convex optimization methods to efficiently locate optimal wideband LNA circuits. The results indicate that the methodology yields significant improvement in key LNA design constraints over existing methodologies while achieving up to one order of magnitude speedup in computational performance.

Field programmable gate arrays (FPGAs) are important hardware platforms in various applications due to increasing design complexity and mask costs. However, as CMOS process technology continues to scale, standard copper interconnect becomes a major bottleneck for FPGA performance. This paper proposed utilizing bundles of single-walled carbon nanotubes (SWCNT) as wires in the FPGA interconnect fabric and compare their performance to standard copper interconnect in future process technologies. To leverage the performance advantages of nanotube-based interconnect, several important aspects of the FPGA routing architecture were explored including the segmentation distribution and the internal population of the wires. The results demonstrate that FPGAs utilizing SWCNT bundle interconnect can achieve a 19% improvement in average area delay product over the best performing architecture for standard copper interconnect in 22 nm process technology

As process technology continues to scale into the nanoscale regime and overall system complexity increases, the reduced order modeling of on-chip interconnect plays a crucial role in determining VLSI system performance. In this paper, we develop an adaptive wavelet interpolation method based on Krylov subspace techniques to generate reduced order interconnect models that are accurate across a wide-range of frequencies. We dynamically select interpolation points by applying an inexpensive Haar wavelet transform and performing irregular sampling in the frequency domain. The results indicate that our method provides greater accuracy than multi-shift Krylov subspace methods with uniform interpolation points.

In this paper, we present a new plasmonic Bragg reflector with high reflectance efficiency in the optical frequency range. This structure is based on dielectric thickness modulation in the metal-insulator-metal (MIM) geometry which provides sub-wavelength light confinement and is suitable for high integration. We investigate and compare the performance of the presented structure with a previously proposed MIM-based reflector. We find that the reflector structures consisting of periodic change in their dielectric materials provide narrow band-gaps, and therefore are more appropriate for filtering applications. On the other hand, with the same effective index contrast, dielectric thickness modulation results in wider band-gaps and higher reflectance at frequencies inside the gap.

The new theory of compressive sensing enables direct analog-to-information conversion of compressible signals at sub-Nyquist acquisition rates. The authors develop new theory, algorithms, performance bounds, and a prototype implementation for an analog-to-information converter based on random demodulation. The architecture is particularly apropos for wideband signals that are sparse in the time-frequency plane. End-to-end simulations of a complete transistor-level implementation prove the concept under the effect of circuit nonidealities.

In this paper, we present a systematic synthesis methodology for fully integrated wideband low noise amplifiers (LNA) that simultaneously optimizes impedance matching, noise figure, and other performance parameters. Leveraging a wideband model, we hierarchically couple global optimization techniques with local convex optimization methods to efficiently locate circuits in the complex design space. The results indicate that the methodology can successfully generate wideband LNAs with various constraints on passive component values and performance metrics while providing the flexibility to reduce the impact of statistical process variations to improve both reliability and yield.

In the nanometer regime, crosstalk significantly impacts the dynamic power consumption of a chip. In this paper, we present a methodology for analyzing crosstalk-induced short-circuit power dissipation in cell-based digital designs. We introduce a new cell pre-characterization technique for facilitating the estimation of crosstalk-induced short-circuit power. Examples demonstrate that the presented methodology is three orders of magnitude faster than circuit simulators while the average error is as low as 3.5%.

In this paper, we present a complete modeling methodology for fully integrated inductively degenerated cascode ultrawideband low noise amplifiers (LNA) with generalized filter-based impedance matching networks. Our accurate analytical models capture the impact of device and passive component parasitics and transistor short channel effects to closely match circuit simulation results. Utilizing our method, we are able to accurately generate an ultrawideband LNA in the 3.1 to 10.6 GHz band using third and fifth order Chebyshev filters as input matching networks. Both of the designs achieve a power gain greater than 9dB, input and output impedance matching less than -9dB, and a noise figure from less than 3.4dB when using a TSMC 0.18μmmixed-signal/RF model. The performance parameters for the third order filter configuration exceed the results reported from previous ultrawideband designs.

Many DSP algorithms are very computationally intensive. They are typically implemented using an ensemble of processing elements (PEs) operating in parallel. The results from PEs need to be communicated with other PEs, and for many applications the cost of implementing the communication between PEs is very high. Given a DSP algorithm with high communication complexity, it is natural to use a network-on-chip (NoC) to implement the communication. We address two key optimization problems that arise in this context - placement, i.e., assigning computations to PEs on the NoC, and scheduling, i.e., constructing a detailed cycle-by-cycle scheme for implementing the communication between PEs on the NoC

In this paper we present SOC-NLNA, a systematic synthesis methodology for fully integrated narrow-band CMOS Low Noise Amplifiers (LNA) in high performance System-on-Chip (SoC) designs. SOC-NLNA is based on deterministic numerical nonlinear optimization and the Normal Boundary Intersection (NBI) method for Pareto optimization. To enable SoC integration, we simultaneously optimize both devices and passive components to yield integrated inductor values that are significantly less than those generated by traditional design techniques. When the synthesized LNAs are simulated using Cadence SpectreRF, SOC-NLNA yields up to 35 and 58 percent improvement in noise figure and gain. Leveraging the efficiency of our methodology, we are able to generate the Pareto surfaces between LNA performance metrics in seconds.

Predicting the performance of the ΕΔΕΔ analog to digital converters (ADCs) is a computationally expensive task that can take several days for estimating the performance. In this paper, we propose a new circuit/behavioral simulation framework for accurately estimating the performance of CT-ΕΔ-ADCs. Our framework is based on newly developed simulation-directed macro-models and associated mapping techniques for accurately modeling and simulating the CT-ΕΔ-ADCs in the presence of the various non-idealities. We validate our circuit/behavioral framework by the simulation of a 2nd order low pass and a 4th order band pass ADCs. Our newly developed framework predicts the performance degradation within an error less than 4% while achieving three orders of magnitude simulation speedup.

In this paper, we present an analytical model for fully integrated CMOS narrow-band low noise amplifiers (LNA) that enables rapid design space exploration during the synthesis process. The analytical model captures the impact of parasitics on passive components and devices to accurately predict both impedance matching and noise figure. Our results indicate that the model provides on average 39.8% better accuracy in noise figure than several current analytical modeling techniques with five orders of magnitude improvement in simulation time when compared with a circuit-level simulator. Given its speed and accuracy, our LNA model is well-suited for design space exploration.

Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper interconnect as technology scales into the nanoscale regime. In this article, we evaluate the performance and reliability of nanotube bundles for both local and global interconnect in future VLSI applications. To provide a holistic evaluation of SWCNT bundles for on-chip interconnect, we have developed an efficient equivalent circuit model that captures the statistical distribution of individual metallic and semiconducting nanotubes while accurately incorporating recent experimental and theoretical results on inductance, contact resistance, and ohmic resistance. Leveraging the circuit model, we examine the performance and reliability of nanotube bundles for both individual signal lines and system-level designs. SWCNT interconnect bundles can provide significant improvement in delay and maximum current density over traditional copper interconnect, depending on bundle geometry and process technology. However, for system-level designs, the statistical variation in the delay of SWCNT bundles may lead to reliability issues in future process technology. Consequently, if the SWCNT chirality can be effectively controlled and other manufacturing challenges are met, SWCNT bundles potentially are a viable alternative to standard copper interconnect as process technology scales.

To successfully design spiral inductors in increasingly complex and integrated mixed-signal systems, effective design automation techniques must be created. In this paper, the authors develop an automated synthesis methodology for integrated spiral inductors to efficiently generate Pareto-optimal designs based on application requirements. At its core, the synthesis approach employs a scalable multilevel single-objective optimization engine that integrates the flexibility of deterministic pattern search optimization with the rapid convergence of local nonlinear convex optimization. Multiobjective optimization techniques and surrogate functions are utilized to approximate Pareto surfaces in the design space to locate Pareto-optimal spiral inductor designs. Using the synthesis methodology, the authors also demonstrate how to reduce the impact of process variation and other sources of modeling error on spiral inductors. The results indicate that the multilevel single-objective optimization engine locates near-optimal spiral inductor geometries with significantly fewer function evaluations than current techniques, whereas the overall synthesis methodology efficiently optimizes inductor designs with an improvement of up to 51% in key design constraints while reducing the impact of process variation and modeling error

This article focuses on the formulation of the substrate resistive coupling using boundary element methods, specifically for substrates without grounded backplates (floating substrates). An accurate and numerically stable formulation is presented. Numerical results are shown to demonstrate the correctness and the numerical robustness of the formulation.

An analytical model for the upper bound of loop self inductance has been developed that is applicable to a wide range of layout geometries commonly encountered in high performance integrated circuits. We demonstrate that the existing analytical models can significantly underestimate the value of loop self inductance producing optimistic results. When compared with field solver results, the developed model shows an average error of 2%. A speedup of more than three orders of magnitude is obtained enabling our model to be fit for applications in inductance screening, inductance aware physical synthesis and prelayout inductance estimation

The efficient optimization of integrated spiral inductors remains a fundamental barrier to the realization of effective analog and mixed-signal design automation. In this paper, we develop a scalable multi-level optimization methodology for spiral inductors that integrates the flexibility of constrained global optimization using Mesh-Adaptive Direct Search (MADS) algorithms with the rapid convergence of local nonlinear convex optimization techniques. Experimental results indicate that our methodology locates optimal spiral inductor geometries with significantly fewer function evaluations than current techniques.

The increasing demand for high performance ICs and system on chip necessitates reliable methodologies for reducing pessimism in chip design. In this paper, we investigate how the frequency dependence of loop self inductance affects the RLC delay. We show that the pessimism in the estimation of RLC propagation delay could be as high as 30% if the frequency dependence of inductance is not considered properly. As a means of efficiently computing less pessimistic RLC delay values, we present an analytical model of frequency dependent loop self inductance that can be applied to model a wide range of real design scenarios. We demonstrate that our approach is computationally efficient and produces accurate and realistic (less pessimistic) delay values that lead to significantly improved system performance.

In order to synthesize spiral inductor designs to meet stringent design requirements, fundamental trade-offs in the design space must be analyzed and exploited. In this paper, we develop a robust automated synthesis methodology to efficiently generate spiral inductor designs using multi-objective optimization techniques and surrogate functions to approximate Pareto surfaces in the design space. Using our synthesis methodology, we also demonstrate how to reduce the impact of process variation and other sources of modeling error on spiral inductors. Our results indicate that our synthesis methodology efficiently optimizes inductor designs based on the application's design requirements with an improvement of up to 51% in key inductor design constraints while reducing the impact of process and model variations.

In this paper we present an improvement to the fictitious magnetic charge approach to computing inductances in the presence of permeable materials. The improvement replaces integration over a "non-piercing" surface with a line integral and an efficient quadrature scheme. Eliminating the need to generate non-piercing surfaces substantially simplifies handling problems with general geometries of permeable materials. Computational results are presented to demonstrate the accuracy and versatility of the new method.

In this paper we present a fast and efficient program for extraction of the frequency dependent inductance of structures with permeable materials. The program, FastMag, uses a magnetic surface charge formulation, efficient techniques for evaluating the required integrals, and a preconditioned GMRES method to solve the resulting linear system. Results from examples are presented to demonstrate the accuracy and versatility of the FastMag program.

With process technology and functional integration advancing steadily, chips are continuing to grow in area while critical dimensions are shrinking. This has led to the emergence of on-chip inductance to be a factor whose effect on performance and on signal integrity has to be managed by chip designers and has to be sometimes traded off against other performance parameters. In this paper, we cover several techniques to reduce on-chip inductance which in turn improve timing predictability and reduce signal delay and crosstalk noise. We present experimental results obtained from simulations of a typical high performance bus structure and a clock tree structure to examine the effectiveness of some of the different inductance reduction techniques.

The goal of this work was to simulate the effect of the finite conductivity of semiconductor substrates on the on-chip coupling inductance and then to investigate the effect of the on-chip coupling inductance on circuit crosstalk. In addition, the limitations of standard approaches for estimating coupling inductance are examined. A method for the reduction of the coupling inductance and its effect on circuit crosstalk is also discussed.

Many physical synthesis tools interdigitate signal and power lines to reduce cross-talk, and thus, improve signal integrity and timing predictability. Such approaches are extremely effective at reducing cross-talk at circuit speeds where inductive effects are inconsequential. In this paper, we use a detailed distributed RLC model to show that inductive cross-talk effects are substantial in long busses associated with 0.18 micron technology. Simulation experiments are then used to demonstrate that cross-talk in such high speed technologies is much better controlled by re-deploying interdigitated power lines to perform differential signaling.

Article Interconnect analysis: from 3-D structures to circuit models Share on Authors: M. Kamon Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile , N. Marques Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile , Y. Massoud Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile , L. Silveira Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile , J. White Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 910–914https://doi.org/10.1145/309847.310097Online:01 June 1999Publication History 8citation278DownloadsMetricsTotal Citations8Total Downloads278Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Because magnetic effects have a much longer spatial range than electrostatic effects, an interconnect line with large inductance will be sensitive to distant variations in interconnect topology. This long range sensitivity makes it difficult to balance delays in nets like clock trees, so for such nets inductance must be minimized. In this paper we use two- and three-dimensional electromagnetic field solvers to compare dedicated ground planes to a less area-consuming approach, interdigitating the signal line with ground lines. The surprising conclusion is that with very little area penalty, interdigitated ground lines are more effective at minimizing self-inductance than ground planes.