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Kazuyoshi Kohno

dblp:27/5023 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2002
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 87% Processor architecture and microarchitecture · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test		 0.012001
A New Verification Methodology for Complex Pipeline Behavior · DAC 2001
Electronic design automation › hardware verification and test › test generation › test case generation
test program generation		 0.012001
A New Verification Methodology for Complex Pipeline Behavior · DAC 2001
Processor architecture and microarchitecture › pipelining
pipeline design		 0.012001
A New Verification Methodology for Complex Pipeline Behavior · DAC 2001

Methods — techniques the papers use, named apart from their topics

test program generation · 0.0
YearPublicationVenuePosition
2002 Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture
abstract
A new integrated system to design and generate a configurable embedded processor for multimedia applications has been developed. The system, "Media embedded Processor Integrator", provides a distinctive feature that generates development tools, such as compilers and simulators, not only for the configurable embedded processor but also for its template based extensible VLIW co-processor. This paper describes the architecture and the function of the "Media embedded Processor Integrator" especially focusing on how the system treats the VLIW co-processor extension. In order to determine an ISA for a 3-way VLIW co-processor for image recognition as an example, several different sets of ISA were evaluated and compared for the best performance using corresponding compilers and simulators, which were generated by the system. The system greatly contributed to reduce this entire ISA definition process.
Atsushi Mizuno, Kazuyoshi Kohno, Ryuichiro Ohyama, Takahiro Tokuyoshi, Hironori Uetani, Hans Eichel, Takashi Miyamori, Nobu Matsumoto, Masataka Matsui
 ICCD2
2001 A New Verification Methodology for Complex Pipeline Behavior
abstract
A new test program generation tool, mVpGen, is developed for verifying pipeline design of microprocessors. The only inputs mVpGen requires are pipeline-behavior specifications; it automatically generates test cases at first from pipeline-behavior specifications and then automatically generates test programs corresponding to the test cases.
Kazuyoshi Kohno, Nobu Matsumoto
 DAC1