In the never-ending quest for performance, multicore processors include a variety of hardware-managed performance-improving components. In this paper, we are mostly interested in components pertaining to the memory subsystem, like prefetch queues, caches, or complex arbiters. We study the case where such components generate or take into account memory access bursts. We show how an explicit modeling of memory traffic burstiness allows significant improvements in the precision of interference analysis. We provide both the formal apparatus for modeling burstiness and dedicated analysis algorithms. Evaluation is performed on one of the few high-performance shared-memory architectures that is welldocumented - the Kalray MPPA3 Coolidge many-core, where our method covers one compute cluster.

We present the first end-to-end modeling and compilation flow to parallelize hard real-time control applications while fully guaranteeing the respect of real-time requirements on off-the-shelf hardware. It scales to thousands of dataflow nodes and has been validated on two production avionics applications. Unlike classical optimizing compilation, it takes as input non-functional requirements (real time, resource limits). To enforce these requirements, the compiler follows a static resource allocation strategy, from coarse-grain tasks communicating over an interconnection network all the way to individual variables and memory accesses. It controls timing interferences resulting from mapping decisions in a precise, safe, and scalable way.

REDEFINE is a distributed dynamic dataflow architecture, designed for exploiting parallelism at various granularities as an embedded system-on-chip (SoC). This paper dwells on the flexibility of REDEFINE architecture and its execution model in accelerating real-time applications coupled with a WCET analyzer that computes execution time bounds of real time applications.

In this paper, we introduce a new formal modeling language that enriches the ground Abstract State Machine (ASM) formalism with the notion of time. Our temporal language is part of a larger HiTAsm language that also features hierarchical abstractions and is custom tailored for WCET analysis. The main differences with other ASM time languages is that HiTAsm correctness is proved using the same ASM metalanguage in which it is later integrated. The main purpose of this paper is to introduce the time in the HiTAsm and to prove its correctness.