Demo Data from VLDB 2026 / reviewers in the wild / expert
Ashwin Prasad
dblp:27/9698
· DBLP profile ↗
4ranked-venue papers
3as first author
2since 2021 · last 2024
0009-0003-9741-9392ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 3 · 2 first-author · 1 since 2021Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Hardware accelerators and domain-specific architectures · 79% GPUs and heterogeneous computing · 21% | |
| Software engineering, system software, and programming languages
3 papers |
Compilers and program optimization · 100% | |
| Artificial intelligence
1 paper |
Kernel, tree and ensemble methods · 100% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization › compiler construction
retargetable compilation |
0.8 | 1 | 2024 | SilvanForge: A Schedule-Guided Retargetable Compiler for Decision Tree Inference · SOSP 2024 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.8 | 1 | 2024 | SilvanForge: A Schedule-Guided Retargetable Compiler for Decision Tree Inference · SOSP 2024 |
Compilers and program optimization
machine learning compiler |
0.6 | 1 | 2022 | Treebeard: An Optimizing Compiler for Decision Tree Based ML Inference · MICRO 2022 |
Hardware accelerators and domain-specific architectures
domain-specific compilers |
0.6 | 1 | 2022 | Treebeard: An Optimizing Compiler for Decision Tree Based ML Inference · MICRO 2022 |
Machine learning › Kernel, tree and ensemble methods › ensemble learning
tree ensembles |
0.2 | 1 | 2022 | Treebeard: An Optimizing Compiler for Decision Tree Based ML Inference · MICRO 2022 |
GPUs and heterogeneous computing › CPU-GPU heterogeneous computing
CPU-GPU co-processing |
0.1 | 1 | 2011 | Automatic compilation of MATLAB programs for synergistic execution on heterogeneous processors · PLDI 2011 |
Compilers and program optimization › parallelization
data parallelism |
0.0 | 1 | 2011 | Automatic compilation of MATLAB programs for synergistic execution on heterogeneous processors · PLDI 2011 |
Methods — techniques the papers use, named apart from their topics
progressive lowering · 1.7SIMD vectorization · 1.7MLIR · 1.7decision tree inference · 1.5data-parallel mapping · 0.2automatic compilation · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | SilvanForge: A Schedule-Guided Retargetable Compiler for Decision Tree InferenceabstractThe proliferation of machine learning together with the rapid evolution of the hardware ecosystem has led to a surge in the demand for model inference on a variety of hardware. Decision tree based models are the most popular models on tabular data. This paper is motivated by the problems encountered when targeting inference of these models to run at peak performance on CPU and GPU targets. Existing solutions are neither portable nor achieve the best possible performance for the specific hardware they target. This is because they do not explore and customize optimization configurations to the target processor and the model being used. Ashwin Prasad, Sampath Rajendra, Kaushik Rajan, R. Govindarajan, Uday Bondhugula |
SOSP | 1 |
| 2022 | Treebeard: An Optimizing Compiler for Decision Tree Based ML InferenceabstractDecision tree ensembles are among the most commonly used machine learning models. These models are used in a wide range of applications and are deployed at scale. Decision tree ensemble inference is usually performed with libraries such as XGBoost, LightGBM, and Sklearn. These libraries incorporate a fixed set of optimizations for the hardware targets they support. However, maintaining these optimizations is prohibitively expensive with the evolution of hardware. Further, they do not specialize the inference code to the model being used, leaving significant performance on the table. This paper presents TREEBEARD, an optimizing compiler that progressively lowers the inference computation to optimized CPU code through multiple intermediate abstractions. By applying model-specific optimizations at the higher levels, tree walk optimizations at the middle level, and machine-specific optimizations lower down, TREEBEARD can specialize inference code for each model on each supported CPU target. TREEBEARD combines several novel optimizations at various abstraction levels to mitigate architectural bottlenecks and enable SIMD vectorization of tree walks. We implement TREEBEARD using the MLIR compiler infrastructure and demonstrate its utility by evaluating it on a diverse set of benchmarks. TREEBEARD is significantly faster than state-of-the-art systems, XGBoost, Treelite and Hummingbird, by 2.6×, 4.7× and 5.4× respectively in a single-core execution setting, and by 2.3×, 2.7× and 14× respectively in multi-core settings. Ashwin Prasad, Sampath Rajendra, Kaushik Rajan, R. Govindarajan, Uday Bondhugula |
MICRO | 1 |
| 2016 | Incremental diagram layout for automated model migration
Ulf Rüegg, Rajneesh Lakkundi, Ashwin Prasad, Anand Kodaganur, Christoph Daniel Schulze, Reinhard von Hanxleden |
MoDELS | 3 |
| 2011 | Automatic compilation of MATLAB programs for synergistic execution on heterogeneous processorsabstractMATLAB is an array language, initially popular for rapid prototyping, but is now being increasingly used to develop production code for numerical and scientific applications. Typical MATLAB programs have abundant data parallelism. These programs also have control flow dominated scalar regions that have an impact on the program's execution time. Today's computer systems have tremendous computing power in the form of traditional CPU cores and throughput oriented accelerators such as graphics processing units(GPUs). Thus, an approach that maps the control flow dominated regions to the CPU and the data parallel regions to the GPU can significantly improve program performance. Ashwin Prasad, Jayvant Anantpur, R. Govindarajan |
PLDI | 1 |