This paper describes a complete hardware implementation of a 24 channel transmultiplexer employing a digital signal processor. The algorithm for the TDM-FDM translation adopted here is a modification of the FFT and digital polyphase method. The modification is mainly directed towards the reduction of roundoff noise, so that the wordlength of the processor can be minimized. In this case, 16 bits for multiplication with double precision accumulation is found to be sufficient to meet the noise requirements as recommended by CCITT G.792. The above modification enables the implementation of the translation algorithm by a 16 bit parallel type digital signal processor. This processor is designed to be firmware controllable and, thus, has a wide range of applications. The entire 24 channel transmultiplexer comprises 1) four signal processors, each handling 12 channels one way translation including signaling; 2) digital interface part to connect to 1.544 Mbit/s PCM system; and 3) codec and Nyquist filter to connect to two 12-channel FDM systems.

A 120-channel transmultiplexer has been developed which interfaces two FDM basic supergroup signals (2 x 60 channels) directly to the digital time division switch or digital transmission systems. The equiplnent exploits a block processing digital SSB-FDM multiplex/demultiplex scheme, and has been built using newly developed high-speed CMOS pipeline multipliers and variable length shift registers. System design considerations and hardware implementation techniques are described in detail as well as the measured performance.