This paper describes a memory-oriented design for a digital transmultiplexer which performs conversion between TDM and FDM on a per-channel basis. The processor uses FIR bandpass filters which also perform interpolation (TDM-to-FDM) and decimation (FDM-to-TDM). Hardware efficiency is obtained by implementing the FIR filters in a logarithmic mode, wherein multiplication becomes addition. Conversions to and from the logarithmic format are done in ROM look-up tables. ROM's are also used to store the filter coefficients. Signal samples are stored in RAM's. This paper describes the architecture of the transmultiplexer and presents simulation results. A TTL laboratory implementation and performance results are presented.