This paper describes the background and the actual circuit designs in the development of the 48-channel modified duobinary PCM line repeater. The reasons for the choice of the modified duobinary coding technique are explained. The equalization requirement of the signal in terms of the channel roll-off factor is obtained by considering the crosstalk penalty, intersymbol interference, and ease of hardware implementation. The hardware implementations of the various repeater sections-equalization, clock recovery, and data regeneration-are outlined. The main considerations in circuit design are circuit size, power consumption, and tolerance to parameter variations. These considerations are of prime importance for the modified duobinary system to retrofit the existing T1 system. Such requirements resulted in the extensive use of integrated circuits and thick-film hybrids and also in the development of a new clock recovery method for a correlative pulse sequence called the "slicer method."