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T. Shimamura

dblp:272/2268 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1977
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Physical-layer communications · 80% Optical networks · 20%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Optical networks › optical transmission impairment
jitter accumulation
0.011977
An Analysis of Jitter Accumulation in a Chain of PLL Timing Recovery Circuits · IEEE Trans. Commun. 1977
Physical-layer communications › synchronization
phase-locked loop
0.011977
An Analysis of Jitter Accumulation in a Chain of PLL Timing Recovery Circuits · IEEE Trans. Commun. 1977
Physical-layer communications › relaying › relay systems
regenerative repeaters
0.011977
An Analysis of Jitter Accumulation in a Chain of PLL Timing Recovery Circuits · IEEE Trans. Commun. 1977
Physical-layer communications › synchronization › timing error
timing jitter
0.011977
An Analysis of Jitter Accumulation in a Chain of PLL Timing Recovery Circuits · IEEE Trans. Commun. 1977
Physical-layer communications › synchronization
timing recovery
0.011977
An Analysis of Jitter Accumulation in a Chain of PLL Timing Recovery Circuits · IEEE Trans. Commun. 1977

Methods — techniques the papers use, named apart from their topics

stochastic jitter analysis · 0.0
YearPublicationVenuePosition
1977 An Analysis of Jitter Accumulation in a Chain of PLL Timing Recovery Circuits
abstract
This paper analyzes the timing jitter accumulation which is produced in a chain of regenerative repeaters when a second-order phase-locked loop (PLL) is used as a timing filter. In a PLL timing recovery circuit, the growth of timing jitter varies with the value of damping factor\zeta. In this paper, therefore, approximate equations of timing jitter accumulation are given with respect to a case in which\zetais sufficiently large, and the timing jitter is calculated with a digital computer for various values of\zeta. It is shown that, when\zetais sufficiently large, results similar to those for first order loops or single tuned circuits are obtained, i.e., the meansquare random jitter is almost proportional to the square root of the number of repeaters, and the mean-square systematic jitter is almost proportional to the number of repeaters. When\zetais small the meansquare jitter increases exponentially as the number of repeaters is increased. This paper also describes the optimum value of\zeta, considering both the jitter accumulation and the transient response of the PLL, by using the number of repeatersNas a parameter. As a result, it is postulated that the optimum value of\zetais 5 to 8 whenNis 100, and 15 to 18 whenNis 1,000.
T. Shimamura, I. Eguchi
IEEE Trans. Commun.1