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Shuxiang Hu

dblp:276/1642 · DBLP profile ↗
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3ranked-venue papers
0as first author
1since 2021 · last 2022
0000-0002-3440-5810ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 100%
Artificial intelligence
1 paper
Deep learning architectures and training · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design
1.432022
Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization · DAC 2020
Electronic design automation › physical design › lithography
layout decomposition
1.022022
Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation › physical design
mask optimization
1.022022
Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation › physical design
optical proximity correction
0.612022
Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
Electronic design automation
design technology co-optimization
0.412020
A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Machine learning › Deep learning architectures and training
convolutional neural network
0.112020
Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization · DAC 2020

Methods — techniques the papers use, named apart from their topics

convolutional neural network · 1.4sampling strategy · 0.9autoencoder · 0.6gradient-based optimization · 0.4discrete optimization · 0.4
YearPublicationVenuePosition
2022 Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization
abstract
Combining multiple patterning lithography (MPL) and optical proximity correction (OPC) pushes the limit of 193-nm wavelength lithography to go further. Considering that layout decomposition may generate plenty of solutions with diverse printabilities, relying on conventional mask optimization (MO) process to select the best candidate for manufacturing is computationally expensive. Therefore, an accurate and efficient printability estimation is crucial and can significantly accelerate the layout decomposition and MO (LDMO) flow. In this article, we propose a convolutional neural network (CNN)-based prediction and integrate it into our new high-performance LDMO framework. The optimization process can be considerably improved as the decomposition quality has been inferred in the early phase. To facilitate the network training and ensure better estimation accuracy, we develop sampling strategies for both layout and decomposition. Moreover, we enhance the layout sampling approach by adopting autoencoder to distance evaluation that promises superior sampling results. The experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.
Shuxiang Hu, Yuzhe Ma, Xiuyuan Ma, Bei Yu 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2020 Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization
abstract
Combining multiple pattern lithography (MPL) and optical proximity correlation (OPC) pushes the limit of 193nm wavelength lithography to go further. Considering that layout decomposition may generate plenty of solutions with diverse printabilities, relying on conventional mask optimization process to select the best candidates for manufacturing is computationally expensive. Therefore, an accurate and efficient printability estimation is crucial and can significantly accelerate the layout decomposition and mask optimization (LDMO) process. In this paper, we propose a CNN based prediction and integrate it into our new high performance LDMO framework. We also develop both the layout and the decomposition sampling strategies to facilitate the network training. The experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.
Shuxiang Hu, Yuzhe Ma, Xiuyuan Ma, Bei Yu 0001
DAC2
2020 A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization
abstract
In advanced technology nodes, layout decomposition (LD) and mask optimization (MO) are two key stages in integrated circuit design. Due to the inconsistency of the objectives of these two stages, the performance of conventional layout and MO may be suboptimal. To tackle this problem, in this article, we propose a unified framework, which seamlessly integrates LD and MO. We propose a gradient-based approach to solve the unified mathematical formulation, as well as a set of discrete optimization techniques to avoid being stuck in local optimum. The conventional optimization process can be accelerated as some inferior decomposition results can be smartly pruned in early stages. The experimental results show that the proposed unified framework can achieve more than 34× speed-up compared with the conventional two-stage flow, meanwhile, it can dramatically reduce EPE violations by more than 8×, and thus maintain better design quality.
Yuzhe Ma, Shuxiang Hu, Jhih-Rong Gao, Jian Kuang 0001, Jin Miao, Bei Yu 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3