As semiconductor manufacturing advances from the 3-nm process toward the sub-nanometer regime and transitions from FinFETs to gate-all-around field-effect transistors (GAAFETs), the resulting complexity and manufacturing challenges continue to increase. In this context, 3D chiplet-based approaches have emerged as key enablers to address these limitations while exploiting the expanded design space. Specifically, chiplets help address the lower yields typically associated with large monolithic designs. This paradigm enables the modular design of heterogeneous systems consisting of multiple chiplets (e.g., CPUs, GPUs, memory) fabricated using different technology nodes and processes. Consequently, it offers a capable and cost-effective strategy for designing heterogeneous systems.This paper introduces the Horizon Europe Twinning project COIN-3D (Collaborative Innovation in 3D VLSI Reliability), which aims to strengthen research excellence in 2.5D/3D VLSI systems reliability through collaboration between leading European institutions. More specifically, our primary scientific goal is the provision of novel open-source Electronic Design Automation (EDA) tools for reliability assessment of 3D systems, integrating advanced algorithms for physical- and system-level reliability analysis.

Architectural exploration of novel technological options, such as 3D integration, requires close interaction with physical implementation. However, the lack of information regarding the technical aspects of the 3D flavor, and lack of open source tools are the key obstacles inhibiting the wide use of physicalaware 3D architectural exploration. To palliate this problem, we present 3DPX, an open-source methodology for 3D physical design exploration based on the OpenROAD framework. By leveraging open standards and tools, our methodology enables evaluation of the impact of 3D stacking on performance, power, and area (PPA). Experimental results on a set of RISC-V benchmark circuits show the expected 50% area reduction, while allowing users to analyze and optimize timing and power just as they would in a traditional 2D flow.

Abstract The aim of this work is to provide a systematic literature review of techniques for taxonomy generation across the cybersecurity domain. Cybersecurity taxonomies can be classified into manual and dynamic, each one of which focuses on different characteristics and tails different goals. Under this premise, we investigate the current state of the art in both categories with respect to their characteristics, applications and methods. To this end, we perform a systematic literature review in accordance with an extensive analysis of the tremendous need for dynamic taxonomies in the cybersecurity landscape. This analysis provides key insights into the advantages and limitations of both techniques, and it discusses the datasets which are most commonly used to generate cybersecurity taxonomies.

In this article, we provide a set of federated learning (FL) protocols for future Internet architectures, which integrate the edge computing with the Internet of Things (IoT) known as “IoT edge computing.” The proposed protocols aim to the efficient implementation of the FL, i.e., distributed intelligence, in future IoT networks, where edge computing will leverage the overall procedure at the edge of the network. We first provide a list of application requirements for such an FL implementation, which result in the architecture of constrained and nonconstrained IoT devices based on a set of Internet engineering task force (IETF) standards. The FL protocols consist of three stages as follows: 1) initial configuration; 2) distributed training; and 3) cloud updates. The specified FL protocols are tested using an experimental IoT platform, which is used to obtain experimental results that provide the performance evaluation of the FL protocols in terms of accuracy, time, and latency. We propose those FL protocols for the next-generation Internet (NGI), where IoT, edge computing, and FL will be blended efficiently for future Internet applications.

Traditional processor architectures utilize an external DRAM for data storage, while they also operate under worst-case timing constraints. Such designs are heavily constrained by the delay costs of the data transfer between the core pipeline and the DRAM, and they are incapable of exploiting the timing variations of their pipeline stages. In this work, we focus on a near-data processing methodology combined with a novel timing analysis technique that enables the adaptive frequency scaling of the core clock and boosts the performance of low-power designs. We propose a near-data processing and better-than-worst-case co-design methodology to efficiently move the instruction execution to the DRAM side and, at the same time, to allow the pipeline to operate at higher clock frequencies compared to the worst-case approach. To this end, we develop a timing analysis technique, which evaluates the timing requirements of individual instructions and we dynamically scale the clock frequency, according to the instructions types that currently occupy the pipeline. We evaluate the proposed methodology on six different RISC-V post-layout implementations using an HMC DRAM to enable the processing-in-memory (PIM) process. Results indicate an average speedup factor of 1.96× with a 1.6× reduction in energy consumption compared to a standard RISC-V PIM baseline implementation.

This paper proposes the cooperative cognitive net-work slicing virtualization solution for smart Internet of things (IoT) applications. To this end, we deploy virtualized small base stations (vSBSs) in SDR devices that offer network-slicing virtualization option. The proposed virtualized solution relies on Fed4Fire wireless experimental platform. In particular, we assume that multiple IoT devices can have access to different vSBSs, which coordinate their resources in a cooperative manner using machine learning (ML). To this end, a proactive resource management is deployed in the unlicensed band, where a cooperative solution is facilitated using the licensed band. The cooperative network slicing is managed and orchestrated using small cell virtualization offered by the Fed4Fire . Experimental trials are carried out for certain number of users and results are obtained that highlight the benefit of employing cooperative cognitive network slicing in future virtualized wireless networks.