Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Suyeon Hur

dblp:276/1914 · DBLP profile ↗
← Back
3ranked-venue papers
1as first author
2since 2021 · last 2023
0000-0002-4831-1137ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Reconfigurable computing and FPGAs · 59% Hardware accelerators and domain-specific architectures · 41%
Artificial intelligence
1 paper
Language models and text generation · 100%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA accelerator
1.122023
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks · ACM Trans. Archit. Code Optim. 2023
Scalable Multi-FPGA Acceleration for Large RNNs with Full Parallelism Levels · DAC 2020
Hardware accelerators and domain-specific architectures
machine learning accelerator
1.122023
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks · ACM Trans. Archit. Code Optim. 2023
Scalable Multi-FPGA Acceleration for Large RNNs with Full Parallelism Levels · DAC 2020
Reconfigurable computing and FPGAs › reconfigurable computing
reconfigurable accelerator
0.712023
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks · ACM Trans. Archit. Code Optim. 2023
Reconfigurable computing and FPGAs › FPGA accelerator
multi-FPGA acceleration
0.412020
Scalable Multi-FPGA Acceleration for Large RNNs with Full Parallelism Levels · DAC 2020
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
RNN accelerator
0.412020
Scalable Multi-FPGA Acceleration for Large RNNs with Full Parallelism Levels · DAC 2020

Methods — techniques the papers use, named apart from their topics

design space exploration · 1.3software pipelining · 0.4collective communication · 0.4RNN partitioning · 0.4
YearPublicationVenuePosition
2023 A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks
abstract
Deep neural networks (DNNs) have become key solutions in the natural language processing (NLP) domain. However, the existing accelerators customized for their narrow target models cannot support diverse NLP models. Therefore, naively running complex NLP models on the existing accelerators often leads to very marginal performance improvements. For these reasons, architects are now in dire need of a new accelerator that can run various NLP models while taking its full performance potential. In this article, we propose FlexRun, an FPGA-based modular accelerator to efficiently support diverse and complex NLP models. First, we identify key components commonly used by NLP models and implement them on top of a current state-of-the-art FPGA-based accelerator. Next, FlexRun conducts an in-depth design space exploration to find the best accelerator architecture for a target NLP model. Last, FlexRun automatically reconfigures the accelerator based on the exploration results. Our FlexRun design outperforms the current state-of-the-art FPGA-based accelerator by 1.21×–2.73× and 1.15×–1.50× for BERT and GPT2, respectively. Compared to Nvidia’s V100 GPU, FlexRun achieves 2.69× higher performance on average for various BERT and GPT2 models.
Suyeon Hur, Seongmin Na, Dongup Kwon, Joonsung Kim 0001, Andrew Boutros, Eriko Nurvitadhi, Jangwoo Kim
ACM Trans. Archit. Code Optim.1
2021 NLP-Fast: A Fast, Scalable, and Flexible System to Accelerate Large-Scale Heterogeneous NLP Models
abstract
Emerging natural language processing (NLP) models have become more complex and bigger to provide more sophisticated NLP services. Accordingly, there is also a strong demand for scalable and flexible computer infrastructure to support these large-scale, complex, and diverse NLP models. However, existing proposals cannot provide enough scalability and flexibility as they neither identify nor optimize a wide spectrum of performance-critical operations appearing in recent NLP models and only focus on optimizing specific operations. In this paper, we propose NLP-Fast, a novel system solution to accelerate a wide spectrum of large-scale NLP models. NLP-Fast mainly consists of two parts: (1) NLP-Perf: an in-depth performance analysis tool to identify critical operations in emerging NLP models and (2) NLP-Opt: three end-to-end optimization techniques to accelerate the identified performance-critical operations on various hardware platforms (e.g., CPU, GPU, FPGA). In this way, NLP-Fast can accelerate various types of NLP models on different hardware platforms by identifying their critical operations through NLP-Perf and applying the NLP-Opt's holistic optimizations. We evaluate NLP-Fast on CPU, GPU, and FPGA, and the overall throughputs are increased by up to 2.92×, 1.59×, and 4.47× over each platform's baseline. We release NLP-Fast to the community so that users are easily able to conduct the NLP-Fast's analysis and apply NLP-Fast's optimizations for their own NLP applications.
Joonsung Kim 0001, Suyeon Hur, Eunbok Lee, Jangwoo Kim
PACT2
2020 Scalable Multi-FPGA Acceleration for Large RNNs with Full Parallelism Levels
abstract
The increasing size of recurrent neural networks (RNNs) makes it hard to meet the growing demand for real-time AI services. For low-latency RNN serving, FPGA-based accelerators can leverage specialized architectures with optimized dataflow. However, they also suffer from severe HW under-utilization when partitioning RNNs, and thus fail to obtain the scalable performance.In this paper, we identify the performance bottlenecks of existing RNN partitioning strategies. Then, we propose a novel RNN partitioning strategy to achieve the scalable multi-FPGA acceleration for large RNNs. First, we introduce three parallelism levels and exploit them by partitioning weight matrices, matrix/vector operations, and layers. Second, we examine the performance impact of collective communications and software pipelining to derive more accurate and optimal distribution results. We prototyped an FPGA-based acceleration system using multiple Intel high-end FPGAs, and our partitioning scheme allows up to 2.4x faster inference of modern RNN workloads than conventional partitioning methods.
Dongup Kwon, Suyeon Hur, Hamin Jang, Eriko Nurvitadhi, Jangwoo Kim
DAC2