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His-Sheng Goan

dblp:276/1976 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 60% Emerging computing paradigms · 40%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
fault modeling
0.412020
Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits · DAC 2020
Electronic design automation › hardware verification and test
fault simulation
0.412020
Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits · DAC 2020
Electronic design automation
hardware verification and test
0.412020
Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits · DAC 2020
Emerging computing paradigms › quantum computer architecture
quantum circuit testing
0.412020
Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits · DAC 2020
Emerging computing paradigms
quantum computer architecture
0.412020
Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits · DAC 2020

Methods — techniques the papers use, named apart from their topics

sparse matrix multiplication · 0.4
YearPublicationVenuePosition
2020 Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits
abstract
Testing for quantum circuits (QC) is a challenging task because QC is intrinsically probabilistic. Existing fault models for QC, such as missing gate faults, are not suitable for quantum dot QC. This paper proposes realistic fault models and fault simulation for quantum dot QC. Our fault models are based on real physical phenomenon of quantum dot devices so that they represent real defect behavior or control errors. Our fault simulation does not need to fully expand gate matrices to 2nx 2n, where n is the number of qubits. Using sparse matrix multiplication, our fault simulation saves a lot of memory and CPU time. We also calculate the test repetition of each test pattern so that we can estimate our test time. Based on fault simulation of a full adder QC, we can select a small test set of six test patterns, totally 526 repetitions, to detect all faults with 99% confidence level.
Cheng-Yun Hsieh, Chen-Hung Wu, Chia-Hsien Huang, His-Sheng Goan, Chien-Mo James Li
DAC4