Modern OoO CPUs employ deep pipelines with high branch misprediction recovery penalties. Instructions speculatively executed along mispredicted paths can significantly alter microarchitectural state. During design space exploration, architects often rely on trace-driven simulators, which are significantly faster than execution-driven models but trade accuracy for speed. Despite this benefit, trace-driven simulation often fails to adequately model the effects of wrong-path execution because traces are typically collected only from the correct-path. While prior work can accurately model wrong-path effects on the instruction stream, it often makes unrealistic assumptions when modeling the impact on the data stream. In this work, we examine the effects of wrong-path execution and present an infrastructure for enabling its modeling in a tracedriven simulator. Our analysis shows that wrong-path execution extensively affects structures on both the instruction and data sides, yielding performance variations ranging from $-3.6 \%$ to $85.7 \%$ compared to a baseline that ignores these effects. To benefit the research community and enhance the accuracy of simulators, we provide our traces and tracing utility. We aim for this to encourage industry to provide wrong-path traces generated by internal simulators, enabling fast academic research without exposing industry proprietary IP.

Modern processors implement a decoupled front-end, often using a form of Fetch Directed Instruction Prefetching (FDIP), to avoid front-end stalls. FDIP is driven by the Branch Prediction Unit (BPU), relying on the BPU's accuracy and branch target tracking structures to speculatively fetch instructions into the Instruction Cache (L1-I cache). As contemporary data center applications become more complex, their code footprints also grow, resulting in a high number of Branch Target Buffer (BTB) misses. These BTB missing branches typically have previously been decoded and placed in the BTB, but have since been evicted, leading to BTB misses now. FDIP can alleviate L1-I cache misses, but its reliance on the BPU's tracking structures means that when it encounters a BTB miss, the BPU may not identify the current instruction as a branch to FDIP. This can prevent FDIP from prefetching or cause it to speculate down the wrong path, further polluting the L1-I cache.

Wi-Fi technology has been thoroughly studied for indoor localization. This is mainly due to the existing infrastructure inside buildings for wireless connectivity and the uptake of mobile devices where Wi-Fi location-dependent measurements, e.g., timing and signal strength readings, are readily available to determine the user location. To enhance the accuracy of Wi-Fi solutions, a two-way ranging approach was recently introduced into the IEEE 802.11 standard for the provision of Fine Timing Measurements (FTM). Such measurements enable a more reliable estimation of the distance between FTM-capable Wi-Fi access points and user-carried devices; thus, promising to deliver meter-level location accuracy. In this work, we propose two novel solutions that leverage FTM and follow different approaches, which have not been investigated in the literature. The first solution is based on an Unscented Kalman Filter (UKF) algorithm to process FTM ranging measurements, while the second solution relies on an FTM fingerprinting method. Experimental results using real-life data collected in a typical office environment demonstrate the effectiveness of both solutions, while the FTM fingerprinting approach demonstrated 1.12m and 2.13m localization errors for the 67-th and 95-th percentiles, respectively. This is a two to three times improvement over the traditional Wi-Fi signal strength fingerprinting approach and the UKF ranging algorithm.