Computation-in-Memory (CIM) has emerged as a promising solution to the memory bottleneck in data-intensive applications and AI accelerators; however, it introduces new testing challenges due to multi-row access patterns and higher sensitivity to variations. These challenges can cause marginal bitcells to fail under CIM operation even if they pass standard March tests, making existing approaches insufficient for ensuring reliable CIM operation. In this work, we propose March-CIM, a modified March test optimized for SRAM-based CIM, which overcomes this limitation. By using read current profiling and a trim-assisted sensing mechanism, our method identifies marginal bitcells that conventional tests miss and selectively subjects them to exhaustive CIM testing to verify their fault-free functionality. This method significantly reduces test time (and thus test cost) by eliminating unnecessary tests for the bitcells with reliable performance. We demonstrate the effectiveness of our CIM test approach using 22 nm FDSOI technology and confirm its compatibility with industrial memory built-in self-test (MBIST) tools with minor modifications, achieving a reduction of up to 67% in test time compared to exhaustive CIM testing. Our method is applicable for field testing to ensure reliable operation through periodically profiling bitcell behavior through MBIST under real-time infield conditions.

Computation-in-memory (CIM) is a promising solution to tackle the memory wall problem in big data and artificial intelligence applications. One possible approach to implement such a scheme is to use nonvolatile resistive memory technologies like spin transfer torque magnetic RAM (STT-MRAM) or resistive RAM (ReRAM). However, despite all the attractive features these technologies offer, they introduce new types of defects different from conventional SRAM technologies. Therefore, there is a need for dedicated testing algorithms that can detect such defects. In this paper, we proposed a testing scheme for CIM-capable memories that utilizes trim circuitry to dynamically switch between standard memory testing and CIM testing modes based on the speed and accuracy requirements, eliminating unnecessary testing overheads. This feature provides significant test time reduction while preserving the quality of the test. The proposed method is compatible with existing memory built-in self-test (MBIST) architecture and can be used for different types of emerging resistive memory technologies.

Biologically-inspired Spiking Neural Networks have emerged as a promising avenue for energy-efficient, high-performance neuromorphic computing. With the demand for highly-customized and cost-effective solutions in emerging application domains like soft robotics, wearables, or IoT-devices, Printed Electronics has emerged as an alternative to traditional silicon technologies leveraging soft materials and flexible substrates. In this paper, we propose an energy-efficient analog printed spiking neuromorphic circuit and a corresponding learning algorithm. Simulations on 13 benchmark datasets show an average of 3.86 x power improvement with similar classification accuracy compared to previous works.

Magnetoresistive random access memory (MRAM) is an attractive option to replace eFlash. The recent demonstration of a nano-second write speed and a 10e14 endurance are compelling performances even as an embedded MRAM for cache replacement. Both eFlash and cache applications often use large array sizes, which require tight defect control. The unique defects in MRAMs that are not easily detectable with traditional memory test algorithms can potentially cause test escapes. Test escapes will not only delay the manufacturing process but also cause reliability issues, which is fatal for safety-critical applications such as automotive. This paper presents effective ways of screening hard-to-find defects related to oxide surface quality. The devices with minor oxide degradation have properties in the grey zone, which spec out some of the properties, although they pass the functional test. We introduce a new test method to screen those spec out cells using read reference trimming.

Testing magnetoresistive random access memory (MRAM) presents several challenges, particularly in scaled technology nodes. One major challenge is the increased interconnect resistance from the bitline and sourceline, which leads to issues like the near-far effect, where bitcells farther from the sensing circuit exhibit higher resistance. Additionally, the fabrication process can result in defects that may not be easily detectable using conventional testing methods. Another factor that makes the screening process more difficult is the presence of process variation. This paper proposes a memory-built-in self-test (MBIST) compatible method that compensates for the interconnect resistance effect using multi-level references and memory partitioning. In addition, the proposed method aims to find the location in the memory array that is less affected by process variation and use it to adjust the screening boundaries for the entire memory to detect defective bitcells more effectively. On average, the proposed method shows around 50% defect coverage improvement and 76% weak bitcell coverage improvement over its previous counterparts. The detected defects will be further evaluated for repair by ECC or other redundancy schemes to maximize product quality and yield.

As technology scales down, the interconnect parasitic resistance more dominantly affects performance degradation and test escapes. The wire resistance increase is especially a great challenge in resistive-based non-volatile memories (NVM) such as magnetic random access memory (MRAM) and resistive RAM (ReRAM) because it can cause faulty reading of the data. The resistive-based NVMs perform the read operation by sensing the bitcell resistance relative to a reference value. Therefore, additive parasitic resistances along the read path, including the bitline (BL) and sourceline (SL) resistances, may cause incorrect read operation. The additive path resistance also makes defect screening harder. A defect screening method designed to detect faulty bitcells located near the sensing circuit may not effectively screen out a bitcell located far from the sensing circuit with the same defectivity level and lead to test escapes. Utilizing a multi-level reference, the proposed new testing scheme compensates for the additive line resistance effect and improves coverage for local defect screening. The detected fault will be further evaluated for correction by ECC or repaired to maximize field coverage. The proposed method is applicable to existing industrial memory built-in self-test (MBIST) solutions with minor modifications.

As we move toward the commercialization of Spin-Transfer Torque Magnetic Random Access Memories (STT -MRAM), cost-effective testing and in-field reliability have become more prominent. Among STT-MRAM manufacturing defects, pinholes are one of the important ones. Pinholes are defects on the surface of the oxide layer which degrade the resistive values and, in some cases, cause an oxide breakdown. Some moderate levels of pinhole defects can remain undetected during standard functional tests and may cause a field failure. A stress test of the whole memory, including multiple cycles of long writes, has been suggested to detect candidate pinhole defects. However, this test not only causes extra costs but also degrades the reliability of MRAM for the entire array. In this paper, we have statistically studied the behavior of pinholes and proposed a cost-effective testing scheme to capture pinhole defects and increase the reliability of the end product. Our method limits the number of test candidate cells that need to be hammered, providing a reduced test time of up to 96.42% for our case studies compared to existing methods. This is while the advantages of standard tests are all preserved with our method. The proposed approach is compatible with memory-built-in self-test (MBIST) schemes.